Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 41400c62 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: mdm: add blsp devices config for mdmcalifornium"

parents a21af975 f2c3be14

arch/arm/boot/dts/qcom/mdmcalifornium-blsp.dtsi

0 → 100644
+375 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

/ {

	aliases {

		i2c1 = &i2c_1;

		i2c2 = &i2c_2;

		i2c3 = &i2c_3;

		i2c4 = &i2c_4;

		spi1 = &spi_1;

		spi2 = &spi_2;

		spi3 = &spi_3;

		spi4 = &spi_4;

	};

};



&soc {

	dma_blsp1: qcom,sps-dma@0x7884000{ /* BLSP1 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";

		reg = <0x7884000 0x23000>;

		interrupts = <0 238 0>;

		qcom,summing-threshold = <0x10>;

	};



	i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78b5000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 95 0>;

		dmas = <&dma_blsp1 8 64 0x20000020 0x20>,

			<&dma_blsp1 9 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

		qcom,master-id = <86>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_1_active>;

		pinctrl-1 = <&i2c_1_sleep>;

		status = "disabled";

	};



	i2c_2: i2c@78B6000 { /* BLSP1 QUP2 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78B6000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 96 0>;

		dmas = <&dma_blsp1 10 64 0x20000020 0x20>,

			<&dma_blsp1 11 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

		qcom,master-id = <86>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_2_active>;

		pinctrl-1 = <&i2c_2_sleep>;

		status = "disabled";

	};



	i2c_3: i2c@78B7000 { /* BLSP1 QUP3 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78B7000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 97 0>;

		dmas = <&dma_blsp1 10 64 0x20000020 0x20>,

			<&dma_blsp1 11 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

		qcom,master-id = <86>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_3_active>;

		pinctrl-1 = <&i2c_3_sleep>;

		status = "disabled";

	};



	i2c_4: i2c@78B8000 { /* BLSP1 QUP4 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78B8000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 98 0>;

		dmas = <&dma_blsp1 14 64 0x20000020 0x20>,

			<&dma_blsp1 15 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

		qcom,master-id = <86>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_4_active>;

		pinctrl-1 = <&i2c_4_sleep>;

		status = "disabled";

	};





	spi_1: spi@78B5000 { /* BLSP1 QUP1 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0x078B5000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 95 0>, <0 238 0>;

		spi-max-frequency = <19200000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <8>;

		qcom,bam-producer-pipe-index = <9>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_1_active>;

		pinctrl-1 = <&spi_1_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;

		status = "disabled";

	};



	spi_2: spi@78B6000 { /* BLSP1 QUP2 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0x78B6000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 96 0>, <0 238 0>;

		spi-max-frequency = <19200000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <10>;

		qcom,bam-producer-pipe-index = <11>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_2_active>;

		pinctrl-1 = <&spi_2_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;

		status = "disabled";

	};



	spi_3: spi@78B7000 { /* BLSP1 QUP3 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0x078B7000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 97 0>, <0 238 0>;

		spi-max-frequency = <19200000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <12>;

		qcom,bam-producer-pipe-index = <13>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_3_active>;

		pinctrl-1 = <&spi_3_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;

		status = "disabled";

	};



	spi_4: spi@78B8000 { /* BLSP1 QUP4 */

		compatible = "qcom,spi-qup-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "spi_physical", "spi_bam_physical";

		reg = <0x078B8000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "spi_irq", "spi_bam_irq";

		interrupts = <0 98 0>, <0 238 0>;

		spi-max-frequency = <19200000>;

		qcom,use-bam;

		qcom,ver-reg-exists;

		qcom,bam-consumer-pipe-index = <14>;

		qcom,bam-producer-pipe-index = <15>;

		qcom,master-id = <86>;

		qcom,use-pinctrl;

		pinctrl-names = "spi_default", "spi_sleep";

		pinctrl-0 = <&spi_4_active>;

		pinctrl-1 = <&spi_4_sleep>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;

		status = "disabled";

	};



	blsp1_uart1_hs: uart@78AF000 { /* BLSP1 UART1 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78AF000 0x200>,

		    <0x7884000 0x23000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart1_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 107 0

			    1 &intc 0 238 0

			    2 &tlmm_pinmux 1 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;



		qcom,bam-tx-ep-pipe-index = <0>;

		qcom,bam-rx-ep-pipe-index = <1>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,

		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart1_sleep>;

		pinctrl-1 = <&blsp1_uart1_active>;



		qcom,msm-bus,name = "buart1";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <86 512 0 0>,

			    <86 512 500 800>;

		status = "disabled";

	};



	blsp1_uart2_hs: uart@78B0000 { /* BLSP1 UART2 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78B0000 0x200>,

		    <0x7884000 0x23000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart2_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 108 0

			    1 &intc 0 238 0

			    2 &tlmm_pinmux 5 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;



		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart2_sleep>;

		pinctrl-1 = <&blsp1_uart2_active>;



		qcom,msm-bus,name = "buart2";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <86 512 0 0>,

			    <86 512 500 800>;

		status = "disabled";

	};



	blsp1_uart3_hs: uart@78B1000 { /* BLSP1 UART3 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78B1000 0x200>,

		    <0x7884000 0x23000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart3_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 109 0

			    1 &intc 0 238 0

			    2 &tlmm_pinmux 9 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;



		qcom,bam-tx-ep-pipe-index = <4>;

		qcom,bam-rx-ep-pipe-index = <5>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,

		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart3_sleep>;

		pinctrl-1 = <&blsp1_uart3_active>;



		qcom,msm-bus,name = "buart3";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <86 512 0 0>,

			    <86 512 500 800>;

		status = "disabled";

	};



	blsp1_uart4_hs: uart@78B2000 { /* BLSP1 UART4 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78B2000 0x200>,

		    <0x7884000 0x23000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart4_hs>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 110 0

			    1 &intc 0 238 0

			    2 &tlmm_pinmux 13 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;



		qcom,bam-tx-ep-pipe-index = <6>;

		qcom,bam-rx-ep-pipe-index = <7>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart4_apps_clk>,

		    <&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart4_sleep>;

		pinctrl-1 = <&blsp1_uart4_active>;



		qcom,msm-bus,name = "buart4";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			    <86 512 0 0>,

			    <86 512 500 800>;

		status = "disabled";

	};

};

arch/arm/boot/dts/qcom/mdmcalifornium-pinctrl.dtsi

+329 −0
Original line number Diff line number Diff line
@@ -44,5 +44,334 @@ 
			};

		};



		/* I2C CONFIGURATION */

		i2c_1 {

			i2c_1_active: i2c_1_active {

				mux {

					pins = "gpio2", "gpio3";

					function = "blsp_i2c1";

				};



				config {

					pins = "gpio2", "gpio3";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_1_sleep: i2c_1_sleep {

				mux {

					pins = "gpio2", "gpio3";

					function = "blsp_i2c1";

				};



				config {

					pins = "gpio2", "gpio3";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		i2c_2 {

			i2c_2_active: i2c_2_active {

				mux {

					pins = "gpio6", "gpio7";

					function = "blsp_i2c2";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_2_sleep: i2c_2_sleep {

				mux {

					pins = "gpio6", "gpio7";

					function = "blsp_i2c2";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		i2c_3 {

			i2c_3_active: i2c_3_active {

				mux {

					pins = "gpio10", "gpio11";

					function = "blsp_i2c3";

				};



				config {

					pins = "gpio10", "gpio11";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_3_sleep: i2c_3_sleep {

				mux {

					pins = "gpio10", "gpio11";

					function = "blsp_i2c3";

				};



				config {

					pins = "gpio10", "gpio11";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		i2c_4 {

			i2c_4_active: i2c_4_active {

				mux {

					pins = "gpio14", "gpio15";

					function = "blsp_i2c4";

				};



				config {

					pins = "gpio14", "gpio15";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c_4_sleep: i2c_4_sleep {

				mux {

					pins = "gpio14", "gpio15";

					function = "blsp_i2c4";

				};



				config {

					pins = "gpio14", "gpio15";

					drive-strength = <2>;

					bias-pull-up;

				};

			};

		};



		/* SPI CONFIGURATION */

		spi_1 {

			spi_1_active: spi_1_active {

				mux {

					pins = "gpio0", "gpio1", "gpio3";

					function = "blsp_spi1";

				};



				config {

					pins = "gpio0", "gpio1", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_1_sleep: spi_1_sleep {

				mux {

					pins = "gpio0", "gpio1", "gpio3";

					function = "blsp_spi1";

				};



				config {

					pins = "gpio0", "gpio1", "gpio3";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_2 {

			spi_2_active: spi_2_active {

				mux {

					pins = "gpio4", "gpio5", "gpio7";

					function = "blsp_spi2";

				};



				config {

					pins = "gpio4", "gpio5", "gpio7";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_2_sleep: spi_2_sleep {

				mux {

					pins = "gpio4", "gpio5", "gpio7";

					function = "blsp_spi2";

				};



				config {

					pins = "gpio4", "gpio5", "gpio7";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_3 {

			spi_3_active: spi_3_active {

				mux {

					pins = "gpio8", "gpio9", "gpio11";

					function = "blsp_spi3";

				};



				config {

					pins = "gpio8", "gpio9", "gpio11";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_3_sleep: spi_3_sleep {

				mux {

					pins = "gpio8", "gpio9", "gpio11";

					function = "blsp_spi3";

				};



				config {

					pins = "gpio8", "gpio9", "gpio11";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		spi_4 {

			spi_4_active: spi_4_active {

				mux {

					pins = "gpio16", "gpio17", "gpio19";

					function = "blsp_spi4";

				};



				config {

					pins = "gpio16", "gpio17", "gpio19";

					drive-strength = <6>;

					bias-disable;

				};

			};



			spi_4_sleep: spi_4_sleep {

				mux {

					pins = "gpio16", "gpio17", "gpio19";

					function = "blsp_spi4";

				};



				config {

					pins = "gpio16", "gpio17", "gpio19";

					drive-strength = <6>;

					bias-disable;

				};

			};

		};



		/* UART HS CONFIGURATION */



		blsp1_uart1_active: blsp1_uart1_active {

			mux {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				function = "blsp_uart2";

			};



			config {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart1_sleep: blsp1_uart1_sleep {

			mux {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				function = "gpio";

			};



			config {

				pins = "gpio0", "gpio1", "gpio2", "gpio3";

				drive-strength = <2>;

				bias-disable;

			};

		};

		blsp1_uart2_active: blsp1_uart2_active {

			mux {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				function = "blsp_uart2";

			};



			config {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart2_sleep: blsp1_uart2_sleep {

			mux {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				function = "gpio";

			};



			config {

				pins = "gpio4", "gpio5", "gpio6", "gpio7";

				drive-strength = <2>;

				bias-disable;

			};

		};

		blsp1_uart3_active: blsp1_uart3_active {

			mux {

				pins = "gpio8", "gpio9", "gpio10", "gpio11";

				function = "blsp_uart2";

			};



			config {

				pins = "gpio8", "gpio9", "gpio10", "gpio11";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart3_sleep: blsp1_uart3_sleep {

			mux {

				pins = "gpio8", "gpio9", "gpio10", "gpio11";

				function = "gpio";

			};



			config {

				pins = "gpio8", "gpio9", "gpio10", "gpio11";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart4_active: blsp1_uart4_active {

			mux {

				pins = "gpio12", "gpio13", "gpio14", "gpio15";

				function = "blsp_uart2";

			};



			config {

				pins = "gpio12", "gpio13", "gpio14", "gpio15";

				drive-strength = <2>;

				bias-disable;

			};

		};



		blsp1_uart4_sleep: blsp1_uart4_sleep {

			mux {

				pins = "gpio12", "gpio13", "gpio14", "gpio15";

				function = "gpio";

			};



			config {

				pins = "gpio12", "gpio13", "gpio14", "gpio15";

				drive-strength = <2>;

				bias-disable;

			};

		};

	};

};

arch/arm/boot/dts/qcom/mdmcalifornium.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ 
#include "mdmcalifornium-regulator.dtsi"

#include "mdmcalifornium-smp2p.dtsi"

#include "msm-gdsc.dtsi"

#include "mdmcalifornium-blsp.dtsi"



&soc {

	#address-cells = <1>;