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Commit 400e68cd authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: update PCIe PHY DUMP sequence for mdmcalifornium



Update the PCIe PHY DUMP sequence for mdmcalifornium based on
new settings while maintaining backward compatibility.

Change-Id: I8711709dee73d9552c911d10a71e2081d789a51b
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 9da4ddc1
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+167 −134
Original line number Original line Diff line number Diff line
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * it under the terms of the GNU General Public License version 2 and
@@ -56,6 +56,7 @@
#define TX_BASE 0x200
#define TX_BASE 0x200
#define RX_BASE 0x400
#define RX_BASE 0x400
#define PCS_BASE 0x800
#define PCS_BASE 0x800
#define PCS_MISC_BASE 0x600
#else
#else
#define PCIE_VENDOR_ID_RCP		0x17cb
#define PCIE_VENDOR_ID_RCP		0x17cb
#define PCIE_DEVICE_ID_RCP		0x0104
#define PCIE_DEVICE_ID_RCP		0x0104
@@ -66,11 +67,13 @@
#define TX_BASE 0x1000
#define TX_BASE 0x1000
#define RX_BASE 0x1200
#define RX_BASE 0x1200
#define PCS_BASE 0x1400
#define PCS_BASE 0x1400
#define PCS_MISC_BASE 0
#endif
#endif


#define TX(n, m) (TX_BASE + n * m * 0x1000)
#define TX(n, m) (TX_BASE + n * m * 0x1000)
#define RX(n, m) (RX_BASE + n * m * 0x1000)
#define RX(n, m) (RX_BASE + n * m * 0x1000)
#define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000)
#define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000)
#define PCS_MISC_PORT(n, m) (PCS_MISC_BASE + n * m * 0x1000)


#define QSERDES_COM_BG_TIMER			0x00C
#define QSERDES_COM_BG_TIMER			0x00C
#define QSERDES_COM_SSC_EN_CENTER		0x010
#define QSERDES_COM_SSC_EN_CENTER		0x010
@@ -141,6 +144,15 @@
#define QSERDES_RX_N_SIGDET_LVL(n, m)			(RX(n, m) + 0x118)
#define QSERDES_RX_N_SIGDET_LVL(n, m)			(RX(n, m) + 0x118)
#define QSERDES_RX_N_RX_BAND(n, m)			(RX(n, m) + 0x120)
#define QSERDES_RX_N_RX_BAND(n, m)			(RX(n, m) + 0x120)


#define PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(n, m)	(PCS_MISC_PORT(n, m) + 0x00)
#define PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(n, m)	(PCS_MISC_PORT(n, m) + 0x04)
#define PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(n, m)	(PCS_MISC_PORT(n, m) + 0x08)
#define PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(n, m)	(PCS_MISC_PORT(n, m) + 0x0C)
#define PCIE_MISC_N_DEBUG_BUS_0_STATUS(n, m)	(PCS_MISC_PORT(n, m) + 0x14)
#define PCIE_MISC_N_DEBUG_BUS_1_STATUS(n, m)	(PCS_MISC_PORT(n, m) + 0x18)
#define PCIE_MISC_N_DEBUG_BUS_2_STATUS(n, m)	(PCS_MISC_PORT(n, m) + 0x1C)
#define PCIE_MISC_N_DEBUG_BUS_3_STATUS(n, m)	(PCS_MISC_PORT(n, m) + 0x20)

#define PCIE_N_SW_RESET(n, m)			(PCS_PORT(n, m) + 0x00)
#define PCIE_N_SW_RESET(n, m)			(PCS_PORT(n, m) + 0x00)
#define PCIE_N_POWER_DOWN_CONTROL(n, m)		(PCS_PORT(n, m) + 0x04)
#define PCIE_N_POWER_DOWN_CONTROL(n, m)		(PCS_PORT(n, m) + 0x04)
#define PCIE_N_START_CONTROL(n, m)		(PCS_PORT(n, m) + 0x08)
#define PCIE_N_START_CONTROL(n, m)		(PCS_PORT(n, m) + 0x08)
@@ -939,182 +951,203 @@ static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
		return true;
		return true;
}
}
#else
#else
static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
static void pcie_phy_dump_test_cntrl(struct msm_pcie_dev_t *dev,
					u32 cntrl4_val, u32 cntrl5_val,
					u32 cntrl6_val, u32 cntrl7_val)
{
{
	int i, size;
	u32 write_val;

	PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx);

	for (i = 0; i < 12; i += 4) {
		write_val = 0x18 + i;
	msm_pcie_write_reg(dev->phy,
	msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy),
		PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy), cntrl4_val);
			write_val);

		write_val++;
	msm_pcie_write_reg(dev->phy,
	msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy),
		PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy), cntrl5_val);
			write_val);

		write_val++;
	msm_pcie_write_reg(dev->phy,
	msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy),
		PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy), cntrl6_val);
			write_val);

		write_val++;
	msm_pcie_write_reg(dev->phy,
	msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy),
		PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy), cntrl7_val);
			write_val);


	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n",
		"PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_TEST_CONTROL4(dev->rc_idx,
			PCIE_N_TEST_CONTROL4(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n",
		"PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_TEST_CONTROL5(dev->rc_idx,
			PCIE_N_TEST_CONTROL5(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n",
		"PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_TEST_CONTROL6(dev->rc_idx,
			PCIE_N_TEST_CONTROL6(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n",
		"PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_TEST_CONTROL7(dev->rc_idx,
			PCIE_N_TEST_CONTROL7(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_PHY_DEBUG_BUS_0_STATUS: 0x%x\n",
		"PCIe: RC%d PCIE_N_DEBUG_BUS_0_STATUS: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
			PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n",
		"PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
			PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n",
		"PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
			PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
	PCIE_DUMP(dev,
	PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n",
		"PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n", dev->rc_idx,
			dev->rc_idx,
		readl_relaxed(dev->phy +
		readl_relaxed(dev->phy +
			PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
			PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
				dev->common_phy)));
				dev->common_phy)));
}
}


	for (i = 0; i < 2; i++) {
static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
		write_val = 0x2 + i;
{
	int i, size;
	u32 write_val;


		msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL,
	PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx);
			write_val);


		PCIE_DUMP(dev,
	pcie_phy_dump_test_cntrl(dev, 0x18, 0x19, 0x1A, 0x1B);
			"PCIe: RC%d to QSERDES_COM_DEBUG_BUS_SEL: 0x%x\n",
	pcie_phy_dump_test_cntrl(dev, 0x1C, 0x1D, 0x1E, 0x1F);
			dev->rc_idx,
	pcie_phy_dump_test_cntrl(dev, 0x20, 0x21, 0x22, 0x23);
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS_SEL));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS0: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS0));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS1: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS1));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS2: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS2));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS3: 0x%x\n\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS3));
	}


	for (i = 0; i < 3; i++) {
	for (i = 0; i < 3; i++) {
		write_val = 0x1 + i;
		write_val = 0x1 + i;

		msm_pcie_write_reg(dev->phy,
		msm_pcie_write_reg(dev->phy,
			QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
			QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
			dev->common_phy),
				dev->common_phy), write_val);
			write_val);
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_TX_N_DEBUG_BUS_SEL: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy +
				QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
					dev->common_phy)));

		pcie_phy_dump_test_cntrl(dev, 0x30, 0x31, 0x32, 0x33);
	}

	pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0);

	if (dev->phy_ver >= 0x10 && dev->phy_ver < 0x20) {
		pcie_phy_dump_test_cntrl(dev, 0x01, 0x02, 0x03, 0x0A);
		pcie_phy_dump_test_cntrl(dev, 0x0E, 0x0F, 0x12, 0x13);
		pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0);

		for (i = 0; i < 8; i += 4) {
			write_val = 0x1 + i;
			msm_pcie_write_reg(dev->phy,
			msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy),
				PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(dev->rc_idx,
			0x30);
					dev->common_phy), write_val);
			msm_pcie_write_reg(dev->phy,
			msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy),
				PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(dev->rc_idx,
			0x31);
					dev->common_phy), write_val + 1);
			msm_pcie_write_reg(dev->phy,
			msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy),
				PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(dev->rc_idx,
			0x32);
					dev->common_phy), write_val + 2);
			msm_pcie_write_reg(dev->phy,
			msm_pcie_write_reg(dev->phy,
			PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy),
				PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(dev->rc_idx,
			0x33);
					dev->common_phy), write_val + 3);


			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n",
				"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_TEST_CONTROL4(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n",
				"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_TEST_CONTROL5(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n",
				"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_TEST_CONTROL6(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n",
				"PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_TEST_CONTROL7(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_PHY_DEBUG_BUS_0_STATUS: 0x%x\n",
				"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_0_STATUS: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_0_STATUS(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n",
				"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_1_STATUS: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_1_STATUS(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n",
				"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_2_STATUS: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_2_STATUS(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
			PCIE_DUMP(dev,
			PCIE_DUMP(dev,
			"PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n",
				"PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_3_STATUS: 0x%x\n",
				dev->rc_idx,
				dev->rc_idx,
				readl_relaxed(dev->phy +
				readl_relaxed(dev->phy +
				PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
					PCIE_MISC_N_DEBUG_BUS_3_STATUS(
				dev->common_phy)));
						dev->rc_idx, dev->common_phy)));
		}

		msm_pcie_write_reg(dev->phy,
			PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(
				dev->rc_idx, dev->common_phy), 0);
		msm_pcie_write_reg(dev->phy,
			PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(
				dev->rc_idx, dev->common_phy), 0);
		msm_pcie_write_reg(dev->phy,
			PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(
				dev->rc_idx, dev->common_phy), 0);
		msm_pcie_write_reg(dev->phy,
			PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(
				dev->rc_idx, dev->common_phy), 0);
	}
	}


	for (i = 0; i < 2; i++) {
		write_val = 0x2 + i;

		msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL,
			write_val);

		PCIE_DUMP(dev,
			"PCIe: RC%d to QSERDES_COM_DEBUG_BUS_SEL: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS_SEL));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS0: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS0));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS1: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS1));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS2: 0x%x\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS2));
		PCIE_DUMP(dev,
			"PCIe: RC%d QSERDES_COM_DEBUG_BUS3: 0x%x\n\n",
			dev->rc_idx,
			readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS3));
	}

	msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL, 0);

	if (dev->common_phy) {
	if (dev->common_phy) {
		msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX,
		msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX,
			0x01);
			0x01);