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Commit 3fc3e1c0 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
Browse files

[ARM] 3333/1: S3C2XX - add dclk and clkout clock support 



Patch from Ben Dooks

Add enable and set_parent calls for the dclk
and clkout clocks.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent a08ceff2

arch/arm/mach-s3c2410/clock.c

+93 −1
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ 
#include <asm/io.h>



#include <asm/arch/regs-clock.h>

#include <asm/arch/regs-gpio.h>



#include "clock.h"

#include "cpu.h"
@@ -285,24 +286,115 @@ static struct clk clk_p = { 


/* clocks that could be registered by external code */



static int s3c24xx_dclk_enable(struct clk *clk, int enable)

{

	unsigned long dclkcon = __raw_readl(S3C2410_DCLKCON);



	if (enable)

		dclkcon |= clk->ctrlbit;

	else

		dclkcon &= ~clk->ctrlbit;



	__raw_writel(dclkcon, S3C2410_DCLKCON);



	return 0;

}



static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)

{

	unsigned long dclkcon;

	unsigned int uclk;



	if (parent == &clk_upll)

		uclk = 1;

	else if (parent == &clk_p)

		uclk = 0;

	else

		return -EINVAL;



	clk->parent = parent;



	dclkcon = __raw_readl(S3C2410_DCLKCON);



	if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {

		if (uclk)

			dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;

		else

			dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;

	} else {

		if (uclk)

			dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;

		else

			dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;

	}



	__raw_writel(dclkcon, S3C2410_DCLKCON);



	return 0;

}





static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)

{

	unsigned long mask;

	unsigned long source;



	/* calculate the MISCCR setting for the clock */



	if (parent == &clk_xtal)

		source = S3C2410_MISCCR_CLK0_MPLL;

	else if (parent == &clk_upll)

		source = S3C2410_MISCCR_CLK0_UPLL;

	else if (parent == &clk_f)

		source = S3C2410_MISCCR_CLK0_FCLK;

	else if (parent == &clk_p)

		source = S3C2410_MISCCR_CLK0_PCLK;

	else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)

		source = S3C2410_MISCCR_CLK0_DCLK0;

	else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)

		source = S3C2410_MISCCR_CLK0_DCLK0;

	else

		return -EINVAL;



	if (clk == &s3c24xx_dclk0)

		mask = S3C2410_MISCCR_CLK0_MASK;

	else {

		source <<= 4;

		mask = S3C2410_MISCCR_CLK1_MASK;

	}



	s3c2410_modify_misccr(mask, source);

	return 0;

}



/* external clock definitions */



struct clk s3c24xx_dclk0 = {

	.name		= "dclk0",

	.id		= -1,

	.ctrlbit	= S3C2410_DCLKCON_DCLK0EN,

	.enable	        = s3c24xx_dclk_enable,

	.set_parent	= s3c24xx_dclk_setparent,

};



struct clk s3c24xx_dclk1 = {

	.name		= "dclk1",

	.id		= -1,

	.ctrlbit	= S3C2410_DCLKCON_DCLK0EN,

	.enable		= s3c24xx_dclk_enable,

	.set_parent	= s3c24xx_dclk_setparent,

};



struct clk s3c24xx_clkout0 = {

	.name		= "clkout0",

	.id		= -1,

	.set_parent	= s3c24xx_clkout_setparent,

};



struct clk s3c24xx_clkout1 = {

	.name		= "clkout1",

	.id		= -1,

	.set_parent	= s3c24xx_clkout_setparent,

};



struct clk s3c24xx_uclk = {
@@ -423,7 +515,7 @@ int s3c24xx_register_clock(struct clk *clk) 


	/* if this is a standard clock, set the usage state */



	if (clk->ctrlbit) {

	if (clk->ctrlbit && clk->enable == s3c24xx_clkcon_enable) {

		unsigned long clkcon = __raw_readl(S3C2410_CLKCON);



		clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0;

include/asm-arm/arch-s3c2410/regs-gpio.h

+2 −0
Original line number Diff line number Diff line
@@ -979,6 +979,7 @@ 
#define S3C2410_MISCCR_CLK0_HCLK    (3<<4)

#define S3C2410_MISCCR_CLK0_PCLK    (4<<4)

#define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)

#define S3C2410_MISCCR_CLK0_MASK    (7<<4)



#define S3C2410_MISCCR_CLK1_MPLL    (0<<8)

#define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
@@ -986,6 +987,7 @@ 
#define S3C2410_MISCCR_CLK1_HCLK    (3<<8)

#define S3C2410_MISCCR_CLK1_PCLK    (4<<8)

#define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)

#define S3C2410_MISCCR_CLK1_MASK    (7<<8)



#define S3C2410_MISCCR_USBSUSPND0   (1<<12)

#define S3C2410_MISCCR_USBSUSPND1   (1<<13)