Merge "msm: clock-cpu-titanium: Introduce a CPU scaling driver for msmtitanium"

Qualcomm MSMTITANIUM CPU clock tree

clock-cpu-titanium is a device that represents the MSMTITANIUM CPU subystem clock

tree. It lists the various power supplies that need to be scaled when the

clocks are scaled and also other HW specific parameters like fmax tables etc.

The root clock generator could have the ramp controller in built.

Ramp control will allow programming the sequence ID for pulse swallowing,

enable sequence and for linking sequence IDs.

Required properties:

- compatible:		Must be "qcom,clock-cpu-titanium".

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Expected

			bases are:

			"c0-pll", "c1-pll", "c0-mux", "c1-mux", "cci-mux",

			"efuse", "perf_base"(optional), "rcgwr-c0-base(optional)",

			"rcgwr-c1-base(optional)".

- clocks:		The clocks sources used by the cluster/cci mux.

- clock-names:		Name of the clocks for the above clocks.

- vdd-mx-supply:	The regulator powering all the PLLs of clusters & cci.

- vdd-cl-supply:	The regulator powering the clusters & cci.

- qcom,speedX-bin-vY-ZZZ:

			A table of CPU frequency (Hz) to voltage (corner)

			mapping that represents the max frequency possible

			for each supported voltage level for a CPU. 'X' is

			the speed bin into which the device falls into - a

			bin will have unique frequency-voltage relationships.

			'Y' is the characterization version, implying that

			characterization (deciding what speed bin a device

			falls into) methods and/or encoding may change. The

			values 'X' and 'Y' are read from efuse registers, and

			the right table is picked from multiple possible tables.

			'ZZZ' can be cl for(c0 & c1) or cci depending on whether

			the table for the clusters or cci.

Example:

	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a412c  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			<          0 0>,

			< 2208000000 7>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  883200000 7>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

obj-$(CONFIG_ARCH_MSM8916)	+= clock-gcc-8952.o

obj-$(CONFIG_ARCH_MSM8916)	+= clock-gcc-titanium.o

obj-$(CONFIG_ARCH_MSM8916)	+= clock-rcgwr.o

obj-$(CONFIG_ARCH_MSM8916)      += clock-cpu-titanium.o

obj-y				+= gdsc.o

obj-y				+= mdss/

#define __MSM_CLOCKS_TITANIUM_H

#define clk_gpll0_clk_src				 0x5933b69f

#define clk_gpll0_ao_clk_src                             0x6b2fb034

#define clk_gpll2_clk_src				 0x7c34503b

#define clk_gpll3_clk_src				 0x5b1eccd5

#define clk_gpll4_clk_src				 0x10525d57

#define clk_gcc_debug_mux				 0x8121ac15

#define clk_wcnss_m_clk					 0x709f430b

#define clk_apcs_hf_pll					 0x8fef0444

#define clk_apcs_hf_pll_main				 0xef871ccf

#define clk_ccissmux					 0x839fb2ef

#define clk_a53_perf_clk				 0xa0a0dc7f

#define clk_a53_pwr_clk					 0x2e6af930

#define clk_a53ssmux_pwr				 0x48a50c99

#define clk_a53ssmux_perf				 0x154acbc9

#define clk_cci_clk					 0x96854074

#define clk_apc0_m_clk					 0xce1e9473

#define clk_apc1_m_clk					 0x990fbaf7

#define clk_cci_m_clk					 0xec7e8afc

#define clk_apss_debug_pri_mux				 0xc691ff55

#define clk_cpu_debug_pri_mux				 0x61a2945f

#endif