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Commit 3f838fc5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'korg/drm-radeon-next' into drm-linus 

This merges all the radeon changes that weren't reliant on core-next.
parents 3ff99164 22dd5013

drivers/gpu/drm/radeon/atombios_crtc.c

+31 −19
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 
{

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);



	switch (mode) {

	case DRM_MODE_DPMS_ON:
@@ -248,20 +249,19 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 
		if (ASIC_IS_DCE3(rdev))

			atombios_enable_crtc_memreq(crtc, 1);

		atombios_blank_crtc(crtc, 0);

		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);

		radeon_crtc_load_lut(crtc);

		break;

	case DRM_MODE_DPMS_STANDBY:

	case DRM_MODE_DPMS_SUSPEND:

	case DRM_MODE_DPMS_OFF:

		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);

		atombios_blank_crtc(crtc, 1);

		if (ASIC_IS_DCE3(rdev))

			atombios_enable_crtc_memreq(crtc, 0);

		atombios_enable_crtc(crtc, 0);

		break;

	}



	if (mode != DRM_MODE_DPMS_OFF) {

		radeon_crtc_load_lut(crtc);

	}

}



static void
@@ -457,9 +457,8 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 
				if (encoder->encoder_type !=

				    DRM_MODE_ENCODER_DAC)

					pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;

				if (!ASIC_IS_AVIVO(rdev)

				    && (encoder->encoder_type ==

					DRM_MODE_ENCODER_LVDS))

				if (encoder->encoder_type ==

					DRM_MODE_ENCODER_LVDS)

					pll_flags |= RADEON_PLL_USE_REF_DIV;

			}

			radeon_encoder = to_radeon_encoder(encoder);
@@ -574,21 +573,34 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 
	struct radeon_device *rdev = dev->dev_private;

	struct radeon_framebuffer *radeon_fb;

	struct drm_gem_object *obj;

	struct drm_radeon_gem_object *obj_priv;

	struct radeon_bo *rbo;

	uint64_t fb_location;

	uint32_t fb_format, fb_pitch_pixels, tiling_flags;

	int r;



	if (!crtc->fb)

		return -EINVAL;

	/* no fb bound */

	if (!crtc->fb) {

		DRM_DEBUG("No FB bound\n");

		return 0;

	}



	radeon_fb = to_radeon_framebuffer(crtc->fb);



	/* Pin framebuffer & get tilling informations */

	obj = radeon_fb->obj;

	obj_priv = obj->driver_private;



	if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {

	rbo = obj->driver_private;

	r = radeon_bo_reserve(rbo, false);

	if (unlikely(r != 0))

		return r;

	r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);

	if (unlikely(r != 0)) {

		radeon_bo_unreserve(rbo);

		return -EINVAL;

	}

	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);

	radeon_bo_unreserve(rbo);

	if (tiling_flags & RADEON_TILING_MACRO)

		fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;



	switch (crtc->fb->bits_per_pixel) {

	case 8:
@@ -618,11 +630,6 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 
		return -EINVAL;

	}



	radeon_object_get_tiling_flags(obj->driver_private,

				       &tiling_flags, NULL);

	if (tiling_flags & RADEON_TILING_MACRO)

		fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;



	if (tiling_flags & RADEON_TILING_MICRO)

		fb_format |= AVIVO_D1GRPH_TILED;
@@ -674,7 +681,12 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 


	if (old_fb && old_fb != crtc->fb) {

		radeon_fb = to_radeon_framebuffer(old_fb);

		radeon_gem_object_unpin(radeon_fb->obj);

		rbo = radeon_fb->obj->driver_private;

		r = radeon_bo_reserve(rbo, false);

		if (unlikely(r != 0))

			return r;

		radeon_bo_unpin(rbo);

		radeon_bo_unreserve(rbo);

	}



	/* Bytes per pixel may have changed */

drivers/gpu/drm/radeon/r100.c

+86 −46
Original line number Diff line number Diff line
@@ -94,6 +94,15 @@ int r100_pci_gart_init(struct radeon_device *rdev) 
	return radeon_gart_table_ram_alloc(rdev);

}



/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */

void r100_enable_bm(struct radeon_device *rdev)

{

	uint32_t tmp;

	/* Enable bus mastering */

	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

	WREG32(RADEON_BUS_CNTL, tmp);

}



int r100_pci_gart_enable(struct radeon_device *rdev)

{

	uint32_t tmp;
@@ -105,9 +114,6 @@ int r100_pci_gart_enable(struct radeon_device *rdev) 
	WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);

	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;

	WREG32(RADEON_AIC_HI_ADDR, tmp);

	/* Enable bus mastering */

	tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

	WREG32(RADEON_BUS_CNTL, tmp);

	/* set PCI GART page-table base address */

	WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);

	tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
@@ -255,24 +261,27 @@ int r100_wb_init(struct radeon_device *rdev) 
	int r;



	if (rdev->wb.wb_obj == NULL) {

		r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,

					 true,

		r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,

					RADEON_GEM_DOMAIN_GTT,

					 false, &rdev->wb.wb_obj);

					&rdev->wb.wb_obj);

		if (r) {

			DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);

			dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);

			return r;

		}

		r = radeon_object_pin(rdev->wb.wb_obj,

				      RADEON_GEM_DOMAIN_GTT,

		r = radeon_bo_reserve(rdev->wb.wb_obj, false);

		if (unlikely(r != 0))

			return r;

		r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,

					&rdev->wb.gpu_addr);

		if (r) {

			DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);

			dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);

			radeon_bo_unreserve(rdev->wb.wb_obj);

			return r;

		}

		r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);

		r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);

		radeon_bo_unreserve(rdev->wb.wb_obj);

		if (r) {

			DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);

			dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);

			return r;

		}

	}
@@ -290,11 +299,19 @@ void r100_wb_disable(struct radeon_device *rdev) 


void r100_wb_fini(struct radeon_device *rdev)

{

	int r;



	r100_wb_disable(rdev);

	if (rdev->wb.wb_obj) {

		radeon_object_kunmap(rdev->wb.wb_obj);

		radeon_object_unpin(rdev->wb.wb_obj);

		radeon_object_unref(&rdev->wb.wb_obj);

		r = radeon_bo_reserve(rdev->wb.wb_obj, false);

		if (unlikely(r != 0)) {

			dev_err(rdev->dev, "(%d) can't finish WB\n", r);

			return;

		}

		radeon_bo_kunmap(rdev->wb.wb_obj);

		radeon_bo_unpin(rdev->wb.wb_obj);

		radeon_bo_unreserve(rdev->wb.wb_obj);

		radeon_bo_unref(&rdev->wb.wb_obj);

		rdev->wb.wb = NULL;

		rdev->wb.wb_obj = NULL;

	}
@@ -1288,17 +1305,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p, 


int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,

					 struct radeon_cs_packet *pkt,

					 struct radeon_object *robj)

					 struct radeon_bo *robj)

{

	unsigned idx;

	u32 value;

	idx = pkt->idx + 1;

	value = radeon_get_ib_value(p, idx + 2);

	if ((value + 1) > radeon_object_size(robj)) {

	if ((value + 1) > radeon_bo_size(robj)) {

		DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "

			  "(need %u have %lu) !\n",

			  value + 1,

			  radeon_object_size(robj));

			  radeon_bo_size(robj));

		return -EINVAL;

	}

	return 0;
@@ -1583,6 +1600,14 @@ void r100_gpu_init(struct radeon_device *rdev) 
	r100_hdp_reset(rdev);

}



void r100_hdp_flush(struct radeon_device *rdev)

{

	u32 tmp;

	tmp = RREG32(RADEON_HOST_PATH_CNTL);

	tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;

	WREG32(RADEON_HOST_PATH_CNTL, tmp);

}



void r100_hdp_reset(struct radeon_device *rdev)

{

	uint32_t tmp;
@@ -1650,6 +1675,17 @@ int r100_gpu_reset(struct radeon_device *rdev) 
	return 0;

}



void r100_set_common_regs(struct radeon_device *rdev)

{

	/* set these so they don't interfere with anything */

	WREG32(RADEON_OV0_SCALE_CNTL, 0);

	WREG32(RADEON_SUBPIC_CNTL, 0);

	WREG32(RADEON_VIPH_CONTROL, 0);

	WREG32(RADEON_I2C_CNTL_1, 0);

	WREG32(RADEON_DVI_I2C_CNTL_1, 0);

	WREG32(RADEON_CAP0_TRIG_CNTL, 0);

	WREG32(RADEON_CAP1_TRIG_CNTL, 0);

}



/*

 * VRAM info
@@ -2594,7 +2630,7 @@ static int r100_cs_track_cube(struct radeon_device *rdev, 
			      struct r100_cs_track *track, unsigned idx)

{

	unsigned face, w, h;

	struct radeon_object *cube_robj;

	struct radeon_bo *cube_robj;

	unsigned long size;



	for (face = 0; face < 5; face++) {
@@ -2607,9 +2643,9 @@ static int r100_cs_track_cube(struct radeon_device *rdev, 


		size += track->textures[idx].cube_info[face].offset;



		if (size > radeon_object_size(cube_robj)) {

		if (size > radeon_bo_size(cube_robj)) {

			DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",

				  size, radeon_object_size(cube_robj));

				  size, radeon_bo_size(cube_robj));

			r100_cs_track_texture_print(&track->textures[idx]);

			return -1;

		}
@@ -2620,7 +2656,7 @@ static int r100_cs_track_cube(struct radeon_device *rdev, 
static int r100_cs_track_texture_check(struct radeon_device *rdev,

				       struct r100_cs_track *track)

{

	struct radeon_object *robj;

	struct radeon_bo *robj;

	unsigned long size;

	unsigned u, i, w, h;

	int ret;
@@ -2676,9 +2712,9 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev, 
				  "%u\n", track->textures[u].tex_coord_type, u);

			return -EINVAL;

		}

		if (size > radeon_object_size(robj)) {

		if (size > radeon_bo_size(robj)) {

			DRM_ERROR("Texture of unit %u needs %lu bytes but is "

				  "%lu\n", u, size, radeon_object_size(robj));

				  "%lu\n", u, size, radeon_bo_size(robj));

			r100_cs_track_texture_print(&track->textures[u]);

			return -EINVAL;

		}
@@ -2700,10 +2736,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 
		}

		size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;

		size += track->cb[i].offset;

		if (size > radeon_object_size(track->cb[i].robj)) {

		if (size > radeon_bo_size(track->cb[i].robj)) {

			DRM_ERROR("[drm] Buffer too small for color buffer %d "

				  "(need %lu have %lu) !\n", i, size,

				  radeon_object_size(track->cb[i].robj));

				  radeon_bo_size(track->cb[i].robj));

			DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",

				  i, track->cb[i].pitch, track->cb[i].cpp,

				  track->cb[i].offset, track->maxy);
@@ -2717,10 +2753,10 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 
		}

		size = track->zb.pitch * track->zb.cpp * track->maxy;

		size += track->zb.offset;

		if (size > radeon_object_size(track->zb.robj)) {

		if (size > radeon_bo_size(track->zb.robj)) {

			DRM_ERROR("[drm] Buffer too small for z buffer "

				  "(need %lu have %lu) !\n", size,

				  radeon_object_size(track->zb.robj));

				  radeon_bo_size(track->zb.robj));

			DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",

				  track->zb.pitch, track->zb.cpp,

				  track->zb.offset, track->maxy);
@@ -2738,11 +2774,12 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 
					  "bound\n", prim_walk, i);

				return -EINVAL;

			}

			if (size > radeon_object_size(track->arrays[i].robj)) {

				DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "

					   "have %lu dwords\n", prim_walk, i,

					   size >> 2,

					   radeon_object_size(track->arrays[i].robj) >> 2);

			if (size > radeon_bo_size(track->arrays[i].robj)) {

				dev_err(rdev->dev, "(PW %u) Vertex array %u "

					"need %lu dwords have %lu dwords\n",

					prim_walk, i, size >> 2,

					radeon_bo_size(track->arrays[i].robj)

					>> 2);

				DRM_ERROR("Max indices %u\n", track->max_indx);

				return -EINVAL;

			}
@@ -2756,10 +2793,12 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 
					  "bound\n", prim_walk, i);

				return -EINVAL;

			}

			if (size > radeon_object_size(track->arrays[i].robj)) {

				DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "

					   "have %lu dwords\n", prim_walk, i, size >> 2,

					   radeon_object_size(track->arrays[i].robj) >> 2);

			if (size > radeon_bo_size(track->arrays[i].robj)) {

				dev_err(rdev->dev, "(PW %u) Vertex array %u "

					"need %lu dwords have %lu dwords\n",

					prim_walk, i, size >> 2,

					radeon_bo_size(track->arrays[i].robj)

					>> 2);

				return -EINVAL;

			}

		}
@@ -3101,6 +3140,9 @@ static int r100_startup(struct radeon_device *rdev) 
{

	int r;



	/* set common regs */

	r100_set_common_regs(rdev);

	/* program mc */

	r100_mc_program(rdev);

	/* Resume clock */

	r100_clock_startup(rdev);
@@ -3108,13 +3150,13 @@ static int r100_startup(struct radeon_device *rdev) 
	r100_gpu_init(rdev);

	/* Initialize GART (initialize after TTM so we can allocate

	 * memory through TTM but finalize after TTM) */

	r100_enable_bm(rdev);

	if (rdev->flags & RADEON_IS_PCI) {

		r = r100_pci_gart_enable(rdev);

		if (r)

			return r;

	}

	/* Enable IRQ */

	rdev->irq.sw_int = true;

	r100_irq_set(rdev);

	/* 1M ring buffer */

	r = r100_cp_init(rdev, 1024 * 1024);
@@ -3174,7 +3216,7 @@ void r100_fini(struct radeon_device *rdev) 
		r100_pci_gart_fini(rdev);

	radeon_irq_kms_fini(rdev);

	radeon_fence_driver_fini(rdev);

	radeon_object_fini(rdev);

	radeon_bo_fini(rdev);

	radeon_atombios_fini(rdev);

	kfree(rdev->bios);

	rdev->bios = NULL;
@@ -3242,10 +3284,8 @@ int r100_init(struct radeon_device *rdev) 
			RREG32(R_0007C0_CP_STAT));

	}

	/* check if cards are posted or not */

	if (!radeon_card_posted(rdev) && rdev->bios) {

		DRM_INFO("GPU not posted. posting now...\n");

		radeon_combios_asic_init(rdev->ddev);

	}

	if (radeon_boot_test_post_card(rdev) == false)

		return -EINVAL;

	/* Set asic errata */

	r100_errata(rdev);

	/* Initialize clocks */
@@ -3264,7 +3304,7 @@ int r100_init(struct radeon_device *rdev) 
	if (r)

		return r;

	/* Memory manager */

	r = radeon_object_init(rdev);

	r = radeon_bo_init(rdev);

	if (r)

		return r;

	if (rdev->flags & RADEON_IS_PCI) {

drivers/gpu/drm/radeon/r100_track.h

+5 −5
Original line number Diff line number Diff line
@@ -10,26 +10,26 @@ 
 * CS functions

 */

struct r100_cs_track_cb {

	struct radeon_object	*robj;

	struct radeon_bo	*robj;

	unsigned		pitch;

	unsigned		cpp;

	unsigned		offset;

};



struct r100_cs_track_array {

	struct radeon_object	*robj;

	struct radeon_bo	*robj;

	unsigned		esize;

};



struct r100_cs_cube_info {

	struct radeon_object	*robj;

	struct radeon_bo	*robj;

	unsigned		offset;

	unsigned		width;

	unsigned		height;

};



struct r100_cs_track_texture {

	struct radeon_object	*robj;

	struct radeon_bo	*robj;

	struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */

	unsigned		pitch;

	unsigned		width;

drivers/gpu/drm/radeon/r300.c

+21 −10
Original line number Diff line number Diff line
@@ -137,14 +137,19 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev) 


void rv370_pcie_gart_disable(struct radeon_device *rdev)

{

	uint32_t tmp;

	u32 tmp;

	int r;



	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);

	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;

	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);

	if (rdev->gart.table.vram.robj) {

		radeon_object_kunmap(rdev->gart.table.vram.robj);

		radeon_object_unpin(rdev->gart.table.vram.robj);

		r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);

		if (likely(r == 0)) {

			radeon_bo_kunmap(rdev->gart.table.vram.robj);

			radeon_bo_unpin(rdev->gart.table.vram.robj);

			radeon_bo_unreserve(rdev->gart.table.vram.robj);

		}

	}

}
@@ -1181,6 +1186,9 @@ static int r300_startup(struct radeon_device *rdev) 
{

	int r;



	/* set common regs */

	r100_set_common_regs(rdev);

	/* program mc */

	r300_mc_program(rdev);

	/* Resume clock */

	r300_clock_startup(rdev);
@@ -1193,13 +1201,18 @@ static int r300_startup(struct radeon_device *rdev) 
		if (r)

			return r;

	}



	if (rdev->family == CHIP_R300 ||

	    rdev->family == CHIP_R350 ||

	    rdev->family == CHIP_RV350)

		r100_enable_bm(rdev);



	if (rdev->flags & RADEON_IS_PCI) {

		r = r100_pci_gart_enable(rdev);

		if (r)

			return r;

	}

	/* Enable IRQ */

	rdev->irq.sw_int = true;

	r100_irq_set(rdev);

	/* 1M ring buffer */

	r = r100_cp_init(rdev, 1024 * 1024);
@@ -1265,7 +1278,7 @@ void r300_fini(struct radeon_device *rdev) 
		r100_pci_gart_fini(rdev);

	radeon_irq_kms_fini(rdev);

	radeon_fence_driver_fini(rdev);

	radeon_object_fini(rdev);

	radeon_bo_fini(rdev);

	radeon_atombios_fini(rdev);

	kfree(rdev->bios);

	rdev->bios = NULL;
@@ -1303,10 +1316,8 @@ int r300_init(struct radeon_device *rdev) 
			RREG32(R_0007C0_CP_STAT));

	}

	/* check if cards are posted or not */

	if (!radeon_card_posted(rdev) && rdev->bios) {

		DRM_INFO("GPU not posted. posting now...\n");

		radeon_combios_asic_init(rdev->ddev);

	}

	if (radeon_boot_test_post_card(rdev) == false)

		return -EINVAL;

	/* Set asic errata */

	r300_errata(rdev);

	/* Initialize clocks */
@@ -1325,7 +1336,7 @@ int r300_init(struct radeon_device *rdev) 
	if (r)

		return r;

	/* Memory manager */

	r = radeon_object_init(rdev);

	r = radeon_bo_init(rdev);

	if (r)

		return r;

	if (rdev->flags & RADEON_IS_PCIE) {

drivers/gpu/drm/radeon/r420.c

+11 −11
Original line number Diff line number Diff line
@@ -169,6 +169,9 @@ static int r420_startup(struct radeon_device *rdev) 
{

	int r;



	/* set common regs */

	r100_set_common_regs(rdev);

	/* program mc */

	r300_mc_program(rdev);

	/* Resume clock */

	r420_clock_resume(rdev);
@@ -186,7 +189,6 @@ static int r420_startup(struct radeon_device *rdev) 
	}

	r420_pipes_init(rdev);

	/* Enable IRQ */

	rdev->irq.sw_int = true;

	r100_irq_set(rdev);

	/* 1M ring buffer */

	r = r100_cp_init(rdev, 1024 * 1024);
@@ -258,7 +260,7 @@ void r420_fini(struct radeon_device *rdev) 
	radeon_agp_fini(rdev);

	radeon_irq_kms_fini(rdev);

	radeon_fence_driver_fini(rdev);

	radeon_object_fini(rdev);

	radeon_bo_fini(rdev);

	if (rdev->is_atom_bios) {

		radeon_atombios_fini(rdev);

	} else {
@@ -301,14 +303,9 @@ int r420_init(struct radeon_device *rdev) 
			RREG32(R_0007C0_CP_STAT));

	}

	/* check if cards are posted or not */

	if (!radeon_card_posted(rdev) && rdev->bios) {

		DRM_INFO("GPU not posted. posting now...\n");

		if (rdev->is_atom_bios) {

			atom_asic_init(rdev->mode_info.atom_context);

		} else {

			radeon_combios_asic_init(rdev->ddev);

		}

	}

	if (radeon_boot_test_post_card(rdev) == false)

		return -EINVAL;



	/* Initialize clocks */

	radeon_get_clock_info(rdev->ddev);

	/* Initialize power management */
@@ -331,10 +328,13 @@ int r420_init(struct radeon_device *rdev) 
		return r;

	}

	/* Memory manager */

	r = radeon_object_init(rdev);

	r = radeon_bo_init(rdev);

	if (r) {

		return r;

	}

	if (rdev->family == CHIP_R420)

		r100_enable_bm(rdev);



	if (rdev->flags & RADEON_IS_PCIE) {

		r = rv370_pcie_gart_init(rdev);

		if (r)