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Commit 3f6065dd authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Kukjin Kim
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ARM: S5P: add required chained_irq_enter/exit to gpio-int code 



This patch adds chained IRQ enter/exit functions to gpio interrupt
handler in order to function correctly on primary controllers with
different methods of flow control.

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 70b0e82b

arch/arm/plat-s5p/irq-gpioint.c

+6 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ 
#include <plat/gpio-core.h>

#include <plat/gpio-cfg.h>



#include <asm/mach/irq.h>



#define GPIO_BASE(chip)		(((unsigned long)(chip)->base) & 0xFFFFF000u)



#define CON_OFFSET		0x700
@@ -81,6 +83,9 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 
	int group, pend_offset, mask_offset;

	unsigned int pend, mask;



	struct irq_chip *chip = irq_get_chip(irq);

	chained_irq_enter(chip, desc);



	for (group = 0; group < bank->nr_groups; group++) {

		struct s3c_gpio_chip *chip = bank->chips[group];

		if (!chip)
@@ -102,6 +107,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 
			pend &= ~BIT(offset);

		}

	}

	chained_irq_exit(chip, desc);

}



static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)