Loading drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +3 −0 Original line number Diff line number Diff line Loading @@ -341,6 +341,9 @@ static inline u32 msm_isp_evt_mask_to_isp_event(u32 evt_mask) case ISP_EVENT_MASK_INDEX_BUF_DIVERT: evt_id = ISP_EVENT_BUF_DIVERT; break; case ISP_EVENT_MASK_INDEX_BUF_DONE: evt_id = ISP_EVENT_BUF_DONE; break; case ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY: evt_id = ISP_EVENT_COMP_STATS_NOTIFY; break; Loading include/media/msmb_isp.h +5 −1 Original line number Diff line number Diff line Loading @@ -536,7 +536,8 @@ enum msm_isp_event_mask_index { ISP_EVENT_MASK_INDEX_SOF = 5, ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, ISP_EVENT_MASK_INDEX_BUF_DONE = 9 }; Loading Loading @@ -569,6 +570,9 @@ enum msm_isp_event_mask_index { #define ISP_EVENT_SUBS_MASK_FE_READ_DONE \ (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) #define ISP_EVENT_SUBS_MASK_BUF_DONE \ (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) enum msm_isp_event_idx { ISP_REG_UPDATE = 0, ISP_EPOCH_0 = 1, Loading Loading
drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +3 −0 Original line number Diff line number Diff line Loading @@ -341,6 +341,9 @@ static inline u32 msm_isp_evt_mask_to_isp_event(u32 evt_mask) case ISP_EVENT_MASK_INDEX_BUF_DIVERT: evt_id = ISP_EVENT_BUF_DIVERT; break; case ISP_EVENT_MASK_INDEX_BUF_DONE: evt_id = ISP_EVENT_BUF_DONE; break; case ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY: evt_id = ISP_EVENT_COMP_STATS_NOTIFY; break; Loading
include/media/msmb_isp.h +5 −1 Original line number Diff line number Diff line Loading @@ -536,7 +536,8 @@ enum msm_isp_event_mask_index { ISP_EVENT_MASK_INDEX_SOF = 5, ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, ISP_EVENT_MASK_INDEX_BUF_DONE = 9 }; Loading Loading @@ -569,6 +570,9 @@ enum msm_isp_event_mask_index { #define ISP_EVENT_SUBS_MASK_FE_READ_DONE \ (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) #define ISP_EVENT_SUBS_MASK_BUF_DONE \ (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) enum msm_isp_event_idx { ISP_REG_UPDATE = 0, ISP_EPOCH_0 = 1, Loading