Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3f0f8670 authored by Linus Walleij's avatar Linus Walleij
Browse files

gpiolib: let gpiochip_add_pin_range() specify offset 



Like with commit 3c739ad0
it is not always enough to specify all the pins of a gpio_chip
from offset zero to be added to a pin map range, since the
mapping from GPIO to pin controller may not be linear at all,
but need to be broken into a few consecutive sub-ranges or
1-pin entries for complicated cases. The ranges may also be
sparse.

This alters the signature of the function to accept offsets
into both the GPIO-chip local pinspace and the pin controller
local pinspace.

Reviewed-by: default avatarStephen Warren <swarren@nvidia.com>
Reviewed-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 5212d096

drivers/gpio/gpiolib-of.c

+12 −0
Original line number Diff line number Diff line
@@ -238,8 +238,20 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) 
		if (!pctldev)

			break;



		/*

		 * This assumes that the n GPIO pins are consecutive in the

		 * GPIO number space, and that the pins are also consecutive

		 * in their local number space. Currently it is not possible

		 * to add different ranges for one and the same GPIO chip,

		 * as the code assumes that we have one consecutive range

		 * on both, mapping 1-to-1.

		 *

		 * TODO: make the OF bindings handle multiple sparse ranges

		 * on the same GPIO chip.

		 */

		ret = gpiochip_add_pin_range(chip,

					     pinctrl_dev_get_name(pctldev),

					     0, /* offset in gpiochip */

					     pinspec.args[0],

					     pinspec.args[1]);

drivers/gpio/gpiolib.c

+29 −3
Original line number Diff line number Diff line
@@ -1187,24 +1187,45 @@ EXPORT_SYMBOL_GPL(gpiochip_find); 


#ifdef CONFIG_PINCTRL



/**

 * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping

 * @chip: the gpiochip to add the range for

 * @pinctrl_name: the dev_name() of the pin controller to map to

 * @offset: the start offset in the current gpio_chip number space

 * @pin_base: the start offset in the pin controller number space

 * @npins: the number of pins from the offset of each pin space (GPIO and

 *	pin controller) to accumulate in this range

 */

int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,

			   unsigned int pin_base, unsigned int npins)

			   unsigned int offset, unsigned int pin_base,

			   unsigned int npins)

{

	struct gpio_pin_range *pin_range;



	pin_range = devm_kzalloc(chip->dev, sizeof(*pin_range), GFP_KERNEL);

	pin_range = kzalloc(sizeof(*pin_range), GFP_KERNEL);

	if (!pin_range) {

		pr_err("%s: GPIO chip: failed to allocate pin ranges\n",

				chip->label);

		return -ENOMEM;

	}



	/* Use local offset as range ID */

	pin_range->range.id = offset;

	pin_range->range.gc = chip;

	pin_range->range.name = chip->label;

	pin_range->range.base = chip->base;

	pin_range->range.base = chip->base + offset;

	pin_range->range.pin_base = pin_base;

	pin_range->range.npins = npins;

	pin_range->pctldev = find_pinctrl_and_add_gpio_range(pinctl_name,

			&pin_range->range);

	if (!pin_range->pctldev) {

		pr_err("%s: GPIO chip: could not create pin range\n",

		       chip->label);

		kfree(pin_range);

	}

	pr_debug("%s: GPIO chip: created GPIO range %d->%d ==> PIN %d->%d\n",

		 chip->label, offset, offset + npins - 1,

		 pin_base, pin_base + npins - 1);



	list_add_tail(&pin_range->node, &chip->pin_ranges);
@@ -1212,6 +1233,10 @@ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 
}

EXPORT_SYMBOL_GPL(gpiochip_add_pin_range);



/**

 * gpiochip_remove_pin_ranges() - remove all the GPIO <-> pin mappings

 * @chip: the chip to remove all the mappings for

 */

void gpiochip_remove_pin_ranges(struct gpio_chip *chip)

{

	struct gpio_pin_range *pin_range, *tmp;
@@ -1220,6 +1245,7 @@ void gpiochip_remove_pin_ranges(struct gpio_chip *chip) 
		list_del(&pin_range->node);

		pinctrl_remove_gpio_range(pin_range->pctldev,

				&pin_range->range);

		kfree(pin_range);

	}

}

EXPORT_SYMBOL_GPL(gpiochip_remove_pin_ranges);

include/asm-generic/gpio.h

+4 −2
Original line number Diff line number Diff line
@@ -283,14 +283,16 @@ struct gpio_pin_range { 
};



int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,

			   unsigned int pin_base, unsigned int npins);

			   unsigned int offset, unsigned int pin_base,

			   unsigned int npins);

void gpiochip_remove_pin_ranges(struct gpio_chip *chip);



#else



static inline int

gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,

		       unsigned int pin_base, unsigned int npins)

		       unsigned int offset, unsigned int pin_base,

		       unsigned int npins)

{

	return 0;

}

include/linux/gpio.h

+2 −1
Original line number Diff line number Diff line
@@ -233,7 +233,8 @@ static inline int irq_to_gpio(unsigned irq) 


static inline int

gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,

		       unsigned int pin_base, unsigned int npins)

		       unsigned int offset, unsigned int pin_base,

		       unsigned int npins)

{

	WARN_ON(1);

	return -EINVAL;