Merge tag 'usb-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

* APM X-Gene 15Gbps Multi-purpose PHY nodes

PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each

PHY (pair of lanes) has its own node.

Required properties:

- compatible		: Shall be "apm,xgene-phy".

- reg			: PHY memory resource is the SDS PHY access resource.

- #phy-cells		: Shall be 1 as it expects one argument for setting

			  the mode of the PHY. Possible values are 0 (SATA),

			  1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).

Optional properties:

- status		: Shall be "ok" if enabled or "disabled" if disabled.

			  Default is "ok".

- clocks		: Reference to the clock entry.

- apm,tx-eye-tuning	: Manual control to fine tune the capture of the serial

			  bit lines from the automatic calibrated position.

			  Two set of 3-tuple setting for each (up to 3)

			  supported link speed on the host. Range from 0 to

			  127 in unit of one bit period. Default is 10.

- apm,tx-eye-direction	: Eye tuning manual control direction. 0 means sample

			  data earlier than the nominal sampling point. 1 means

			  sample data later than the nominal sampling point.

			  Two set of 3-tuple setting for each (up to 3)

			  supported link speed on the host. Default is 0.

- apm,tx-boost-gain	: Frequency boost AC (LSB 3-bit) and DC (2-bit)

			  gain control. Two set of 3-tuple setting for each

			  (up to 3) supported link speed on the host. Range is

			  between 0 to 31 in unit of dB. Default is 3.

- apm,tx-amplitude	: Amplitude control. Two set of 3-tuple setting for

			  each (up to 3) supported link speed on the host.

			  Range is between 0 to 199500 in unit of uV.

			  Default is 199500 uV.

- apm,tx-pre-cursor1	: 1st pre-cursor emphasis taps control. Two set of

			  3-tuple setting for each (up to 3) supported link

			  speed on the host. Range is 0 to 273000 in unit of

			  uV. Default is 0.

- apm,tx-pre-cursor2	: 2st pre-cursor emphasis taps control. Two set of

			  3-tuple setting for each (up to 3) supported link

			  speed on the host. Range is 0 to 127400 in unit uV.

			  Default is 0x0.

- apm,tx-post-cursor	: Post-cursor emphasis taps control. Two set of

			  3-tuple setting for Gen1, Gen2, and Gen3. Range is

			  between 0 to 0x1f in unit of 18.2mV. Default is 0xf.

- apm,tx-speed		: Tx operating speed. One set of 3-tuple for each

			  supported link speed on the host.

			   0 = 1-2Gbps

			   1 = 2-4Gbps (1st tuple default)

			   2 = 4-8Gbps

			   3 = 8-15Gbps (2nd tuple default)

			   4 = 2.5-4Gbps

			   5 = 4-5Gbps

			   6 = 5-6Gbps

			   7 = 6-16Gbps (3rd tuple default)

NOTE: PHY override parameters are board specific setting.

Example:

		phy1: phy@1f21a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f21a000 0x0 0x100>;

			#phy-cells = <1>;

			status = "disabled";

		};

		phy2: phy@1f22a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f22a000 0x0 0x100>;

			#phy-cells = <1>;

			status = "ok";

		};

		phy3: phy@1f23a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f23a000 0x0 0x100>;

			#phy-cells = <1>;

			status = "ok";

		};

- compatible : should be "samsung,exynos5250-dp-video-phy";

- reg : offset and length of the Display Port PHY register set;

- #phy-cells : from the generic PHY bindings, must be 0;

Samsung S5P/EXYNOS SoC series USB PHY

-------------------------------------------------

Required properties:

- compatible : should be one of the listed compatibles:

	- "samsung,exynos4210-usb2-phy"

	- "samsung,exynos4x12-usb2-phy"

	- "samsung,exynos5250-usb2-phy"

- reg : a list of registers used by phy driver

	- first and obligatory is the location of phy modules registers

- samsung,sysreg-phandle - handle to syscon used to control the system registers

- samsung,pmureg-phandle - handle to syscon used to control PMU registers

- #phy-cells : from the generic phy bindings, must be 1;

- clocks and clock-names:

	- the "phy" clock is required by the phy module, used as a gate

	- the "ref" clock is used to get the rate of the clock provided to the

	  PHY module

The first phandle argument in the PHY specifier identifies the PHY, its

meaning is compatible dependent. For the currently supported SoCs (Exynos 4210

and Exynos 4212) it is as follows:

  0 - USB device ("device"),

  1 - USB host ("host"),

  2 - HSIC0 ("hsic0"),

  3 - HSIC1 ("hsic1"),

Exynos 4210 and Exynos 4212 use mode switching and require that mode switch

register is supplied.

Example:

For Exynos 4412 (compatible with Exynos 4212):

usbphy: phy@125b0000 {

	compatible = "samsung,exynos4x12-usb2-phy";

	reg = <0x125b0000 0x100>;

	clocks = <&clock 305>, <&clock 2>;

	clock-names = "phy", "ref";

	status = "okay";

	#phy-cells = <1>;

	samsung,sysreg-phandle = <&sys_reg>;

	samsung,pmureg-phandle = <&pmu_reg>;

};

Then the PHY can be used in other nodes such as:

phy-consumer@12340000 {

	phys = <&usbphy 2>;

	phy-names = "phy";

};

Refer to DT bindings documentation of particular PHY consumer devices for more

information about required PHYs and the way of specification.

Allwinner sun4i USB PHY

-----------------------

Required properties:

- compatible : should be one of "allwinner,sun4i-a10-usb-phy",

  "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"

- reg : a list of offset + length pairs

- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"

- #phy-cells : from the generic phy bindings, must be 1

- clocks : phandle + clock specifier for the phy clock

- clock-names : "usb_phy"

- resets : a list of phandle + reset specifier pairs

- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"

Example:

	usbphy: phy@0x01c13400 {

		#phy-cells = <1>;

		compatible = "allwinner,sun4i-a10-usb-phy";

		/* phy base regs, phy1 pmu reg, phy2 pmu reg */

		reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;

		reg-names = "phy_ctrl", "pmu1", "pmu2";

		clocks = <&usb_clk 8>;

		clock-names = "usb_phy";

		resets = <&usb_clk 1>, <&usb_clk 2>;

		reset-names = "usb1_reset", "usb2_reset";

	};

USB PHY

TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs

OMAP CONTROL PHY

Required properties:

 - compatible: Should be one of

 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.

 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register

                        e.g. USB2_PHY on OMAP5.

 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control

                        e.g. USB3 PHY and SATA PHY on OMAP5.

 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on

                        DRA7 platform.

 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on

                        AM437 platform.

 - reg : Address and length of the register set for the device. It contains

   the address of "otghs_control" for control-phy-otghs or "power" register

   for other types.

 - reg-names: should be "otghs_control" control-phy-otghs and "power" for

   other types.

omap_control_usb: omap-control-usb@4a002300 {

        compatible = "ti,control-phy-otghs";

        reg = <0x4a00233c 0x4>;

        reg-names = "otghs_control";

};

OMAP USB2 PHY

	#phy-cells = <0>;

};

OMAP USB3 PHY

TI PIPE3 PHY

Required properties:

 - compatible: Should be "ti,omap-usb3"

 - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".

   "ti,omap-usb3" is deprecated.

 - reg : Address and length of the register set for the device.

 - reg-names: The names of the register addresses corresponding to the registers

   filled in "reg".

 - #phy-cells: determine the number of cells that should be given in the

   phandle while referencing this phy.

 - clocks: a list of phandles and clock-specifier pairs, one for each entry in

   clock-names.

 - clock-names: should include:

   * "wkupclk" - wakeup clock.

   * "sysclk" - system clock.

   * "refclk" - reference clock.

Optional properties:

 - ctrl-module : phandle of the control module used by PHY driver to power on

This is usually a subnode of ocp2scp to which it is connected.

usb3phy@4a084400 {

	compatible = "ti,omap-usb3";

	compatible = "ti,phy-usb3";

	reg = <0x4a084400 0x80>,

	      <0x4a084800 0x64>,

	      <0x4a084c00 0x40>;

	reg-names = "phy_rx", "phy_tx", "pll_ctrl";

	ctrl-module = <&omap_control_usb>;

	#phy-cells = <0>;

	clocks = <&usb_phy_cm_clk32k>,

		 <&sys_clkin>,

		 <&usb_otg_ss_refclk960m>;

	clock-names =	"wkupclk",

			"sysclk",

			"refclk";

};

- vbus-supply: regulator for vbus

- disable-over-current: disable over current detect

- external-vbus-divider: enables off-chip resistor divider for Vbus

- maximum-speed: limit the maximum connection speed to "full-speed".

Examples:

usb@02184000 { /* USB OTG */

	fsl,usbmisc = <&usbmisc 0>;

	disable-over-current;

	external-vbus-divider;

	maximum-speed = "full-speed";

};