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Commit 3e594ce7 authored by Kiran AVND's avatar Kiran AVND Committed by Mauro Carvalho Chehab
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[media] s5p-mfc: Core support for v8 encoder 



This patch adds core support for v8 encoder. This
patch also adds register definitions and buffer size
requirements for H264 & VP8 encoding, needed for new
firmware version v8 for MFC

Signed-off-by: default avatarKiran AVND <avnd.kiran@samsung.com>
Signed-off-by: default avatarPawel Osciak <posciak@chromium.org>
Signed-off-by: default avatarArun Kumar K <arun.kk@samsung.com>
[k.debski@samsung.com: Change MFC version macro name to MFC_V8_BIT]
Signed-off-by: default avatarKamil Debski <k.debski@samsung.com>

Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent e2b9deb2

drivers/media/platform/s5p-mfc/regs-mfc-v8.h

+30 −0
Original line number Diff line number Diff line
@@ -72,16 +72,46 @@ 
/* SEI related information */

#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8	0xf6dc



/* Encoder Registers */

#define S5P_FIMV_E_FIXED_PICTURE_QP_V8		0xf794

#define S5P_FIMV_E_RC_CONFIG_V8			0xf798

#define S5P_FIMV_E_RC_QP_BOUND_V8		0xf79c

#define S5P_FIMV_E_RC_RPARAM_V8			0xf7a4

#define S5P_FIMV_E_MB_RC_CONFIG_V8		0xf7a8

#define S5P_FIMV_E_PADDING_CTRL_V8		0xf7ac

#define S5P_FIMV_E_MV_HOR_RANGE_V8		0xf7b4

#define S5P_FIMV_E_MV_VER_RANGE_V8		0xf7b8



#define S5P_FIMV_E_VBV_BUFFER_SIZE_V8		0xf78c

#define S5P_FIMV_E_VBV_INIT_DELAY_V8		0xf790



#define S5P_FIMV_E_ASPECT_RATIO_V8		0xfb4c

#define S5P_FIMV_E_EXTENDED_SAR_V8		0xfb50

#define S5P_FIMV_E_H264_OPTIONS_V8		0xfb54



/* MFCv8 Context buffer sizes */

#define MFC_CTX_BUF_SIZE_V8		(30 * SZ_1K)	/*  30KB */

#define MFC_H264_DEC_CTX_BUF_SIZE_V8	(2 * SZ_1M)	/*  2MB */

#define MFC_OTHER_DEC_CTX_BUF_SIZE_V8	(20 * SZ_1K)	/*  20KB */

#define MFC_H264_ENC_CTX_BUF_SIZE_V8	(100 * SZ_1K)	/* 100KB */

#define MFC_OTHER_ENC_CTX_BUF_SIZE_V8	(10 * SZ_1K)	/*  10KB */



/* Buffer size defines */

#define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h)	(((w) + 1) * ((h) + 1) * 8)



#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h)	(((w) * 704) + 2176)

#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \

		(((w) * 576 + (h) * 128)  + 4128)



#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \

			(((w) * 592) + 2336)

#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \

			(((w) * 576) + 10512 + \

			((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))

#define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \

	((DIV_ROUND_UP((mbw * 16), 64) *  DIV_ROUND_UP((mbh * 16), 64) * 256) \

	 + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16))



/* BUffer alignment defines */

#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8	64

drivers/media/platform/s5p-mfc/s5p_mfc.c

+2 −0
Original line number Diff line number Diff line
@@ -1404,6 +1404,8 @@ struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = { 
	.dev_ctx	= MFC_CTX_BUF_SIZE_V8,

	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V8,

	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V8,

	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V8,

	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V8,

};



struct s5p_mfc_buf_size buf_size_v8 = {

drivers/media/platform/s5p-mfc/s5p_mfc_enc.c

+11 −6
Original line number Diff line number Diff line
@@ -58,7 +58,8 @@ static struct s5p_mfc_fmt formats[] = { 
		.codec_mode	= S5P_MFC_CODEC_NONE,

		.type		= MFC_FMT_RAW,

		.num_planes	= 2,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |

								MFC_V8_BIT,

	},

	{

		.name		= "4:2:0 2 Planes Y/CrCb",
@@ -66,7 +67,8 @@ static struct s5p_mfc_fmt formats[] = { 
		.codec_mode	= S5P_MFC_CODEC_NONE,

		.type		= MFC_FMT_RAW,

		.num_planes	= 2,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |

								MFC_V8_BIT,

	},

	{

		.name		= "H264 Encoded Stream",
@@ -74,7 +76,8 @@ static struct s5p_mfc_fmt formats[] = { 
		.codec_mode	= S5P_MFC_CODEC_H264_ENC,

		.type		= MFC_FMT_ENC,

		.num_planes	= 1,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |

								MFC_V8_BIT,

	},

	{

		.name		= "MPEG4 Encoded Stream",
@@ -82,7 +85,8 @@ static struct s5p_mfc_fmt formats[] = { 
		.codec_mode	= S5P_MFC_CODEC_MPEG4_ENC,

		.type		= MFC_FMT_ENC,

		.num_planes	= 1,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |

								MFC_V8_BIT,

	},

	{

		.name		= "H263 Encoded Stream",
@@ -90,7 +94,8 @@ static struct s5p_mfc_fmt formats[] = { 
		.codec_mode	= S5P_MFC_CODEC_H263_ENC,

		.type		= MFC_FMT_ENC,

		.num_planes	= 1,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT,

		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |

								MFC_V8_BIT,

	},

	{

		.name		= "VP8 Encoded Stream",
@@ -98,7 +103,7 @@ static struct s5p_mfc_fmt formats[] = { 
		.codec_mode	= S5P_MFC_CODEC_VP8_ENC,

		.type		= MFC_FMT_ENC,

		.num_planes	= 1,

		.versions	= MFC_V7_BIT,

		.versions	= MFC_V7_BIT | MFC_V8_BIT,

	},

};

drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c

+47 −9
Original line number Diff line number Diff line
@@ -77,6 +77,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) 
			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);

		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);

	} else if (ctx->type == MFCINST_ENCODER) {

		if (IS_MFCV8(dev))

			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *

			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),

			S5P_FIMV_TMV_BUFFER_ALIGN_V6);

		else

			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *

			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),

			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
@@ -87,6 +92,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) 
		ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *

				S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,

				S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);

		if (IS_MFCV8(dev))

			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(

						ctx->img_width, ctx->img_height,

						mb_width, mb_height),

						S5P_FIMV_ME_BUFFER_ALIGN_V6);

		else

			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(

						ctx->img_width, ctx->img_height,

						mb_width, mb_height),
@@ -174,6 +185,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) 
		ctx->bank1.size = ctx->scratch_buf_size;

		break;

	case S5P_MFC_CODEC_H264_ENC:

		if (IS_MFCV8(dev))

			ctx->scratch_buf_size =

				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(

					mb_width,

					mb_height);

		else

			ctx->scratch_buf_size =

				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(

						mb_width,
@@ -201,6 +218,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) 
		ctx->bank2.size = 0;

		break;

	case S5P_MFC_CODEC_VP8_ENC:

		if (IS_MFCV8(dev))

			ctx->scratch_buf_size =

				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(

					mb_width,

					mb_height);

		else

			ctx->scratch_buf_size =

				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(

						mb_width,
@@ -2235,6 +2258,21 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) 
	R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);

	R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);



	/* encoder registers */

	R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);

	R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);

	R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);

	R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);

	R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);

	R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);

	R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);

	R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);

	R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);

	R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);

	R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);

	R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);

	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);



done:

	return &mfc_regs;

#undef S5P_MFC_REG_ADDR