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Commit 3df7f8d6 authored by Subhash Jadavani's avatar Subhash Jadavani
Browse files

clk: msm: clock-gcc-8996: add BCR for gcc_ufs_axi_clk 



It is required to reset the UFS block for error handling. This
patch adds support for UFS block level reset.

Change-Id: Ia26cbdb8f7bf259e836052931cb9d5e2d238b471
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 861a4ae9

drivers/clk/msm/clock-gcc-8996.c

+1 −0
Original line number Diff line number Diff line
@@ -2642,6 +2642,7 @@ static struct branch_clk gcc_ufs_ahb_clk = { 
};



static struct branch_clk gcc_ufs_axi_clk = {

	.bcr_reg = GCC_UFS_BCR,

	.cbcr_reg = GCC_UFS_AXI_CBCR,

	.has_sibling = 0,

	.base = &virt_base,

include/dt-bindings/clock/msm-clocks-hwio-8996.h

+1 −0
Original line number Diff line number Diff line
@@ -394,6 +394,7 @@ 
#define GCC_GP3_CBCR						(0x66000)

#define GCC_GP3_CMD_RCGR					(0x66004)

#define GCC_GPLL4_MODE						(0x77000)

#define GCC_UFS_BCR						(0x75000)

#define GCC_UFS_AXI_CBCR					(0x75008)

#define GCC_UFS_AHB_CBCR					(0x7500C)

#define GCC_UFS_TX_CFG_CBCR					(0x75010)