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Commit 3d97269c authored by Puneet Mishra's avatar Puneet Mishra
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ARM: dts: msm: Add mcd device tree data for msm8952 



Add the MCD device tree data to dts files by adding mcd device
node with all the necessary parameters.

Change-Id: I43f63528ca06b41ba740d2716bc5b6cf64eee57d
Acked-by: default avatarTony Hamilton <tonyh@qti.qualcomm.com>
Signed-off-by: default avatarPuneet Mishra <puneetm@codeaurora.org>
parent 630fdcc6

Documentation/devicetree/bindings/mcd/mcd.txt

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+29 −0
Original line number Diff line number Diff line 
* MCD (MobiCore Driver)



t-base is an operating system running in the secure world (TrustZone).

The t-base implementation consists of several components in the

secure world and the non-secure world (kernel and user space). The

MobiCore driver communicates with the t-base operating system that

exists in TrustZone.



Required properties:

  - compatible: Should be "qcom,mcd"

  - qcom,ce-hw-instance: should contain crypto HW instance

  - qcom,ce-device: Device number

  - clocks: Array of <clock_controller_phandle clock_reference> listing

            all the clocks that are accesed by this subsystem.

  - qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.



Example:

	mcd {

		compatible = "qcom,mcd";

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

	};

arch/arm/boot/dts/qcom/msm8952.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -2187,6 +2187,20 @@ 
			reg = <0x45>;

		};

	};



	mcd {

		compatible = "qcom,mcd";

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

	};



};



&gdsc_venus {