Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3cd1f376 authored by Max Filippov's avatar Max Filippov Committed by Sasha Levin
Browse files

spi: xtensa-xtfpga: fix register endianness 



[ Upstream commit b0b4855099e301c8603ea37da9a0103a96c2e0b1 ]

XTFPGA SPI controller has native endian registers.
Fix register acessors so that they work in big-endian configurations.

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 9ab87815

drivers/spi/spi-xtensa-xtfpga.c

+2 −2
Original line number Diff line number Diff line
@@ -34,13 +34,13 @@ struct xtfpga_spi { 
static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,

				      unsigned addr, u32 val)

{

	iowrite32(val, spi->regs + addr);

	__raw_writel(val, spi->regs + addr);

}



static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,

					     unsigned addr)

{

	return ioread32(spi->regs + addr);

	return __raw_readl(spi->regs + addr);

}



static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)