Loading arch/arm/boot/dts/qcom/msm8996.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -2438,7 +2438,7 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 3936000 393600>; <55 512 393600 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_gcc clk_qcrypto_ce1_clk>, Loading Loading @@ -2468,7 +2468,7 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 3936000 393600>; <55 512 393600 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_gcc clk_qcedev_ce1_clk>, Loading Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -2438,7 +2438,7 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 3936000 393600>; <55 512 393600 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_gcc clk_qcrypto_ce1_clk>, Loading Loading @@ -2468,7 +2468,7 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 3936000 393600>; <55 512 393600 393600>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; clocks = <&clock_gcc clk_qcedev_ce1_clk>, Loading