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Commit 3cb14278 authored by Tirupathi Reddy's avatar Tirupathi Reddy
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regulator: cpr3: mark cpr core_clk optional



On some targets the CPR core_clk is not required to be
explicitly configured. Make this clock optional.

Change-Id: Idb659952db7c636cff81c93a578c5d4498c295fa
Signed-off-by: default avatarTirupathi Reddy <tirupath@codeaurora.org>
parent 2f867742
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+8 −7
Original line number Diff line number Diff line
@@ -74,20 +74,21 @@ Platform independent properties:
		    after increasing the vdd-supply voltage.

- clocks
	Usage:      required
	Usage:      optional
	Value type: <prop-encoded-array>
	Definition: Array of clock tuples in which each tuple consists of a
		    phandle to a clock device and a clock ID number. The CPR3
		    core clock must be specified.  See platform specific
		    cpr3-regulator binding documentation for additional clocks
		    that may also need to be specified.
		    core clock must be specified for some targets. See platform
		    specific cpr3-regulator binding documentation for additional
		    clocks that may also need to be specified.

- clock-names
	Usage:      required
	Usage:      optional
	Value type: <stringlist>
	Definition: Clock names.  This list must match up 1-to-1 with the clocks
		    specified in the 'clocks' property. "core_clk" must be
		    specified.  Other clocks may be required for some platforms.
		    specified for some platforms. Other clocks may be required
		    for some platforms.

- interrupts
	Usage:      required
+7 −8
Original line number Diff line number Diff line
@@ -473,12 +473,14 @@ static int cpr3_regulator_init_ctrl(struct cpr3_controller *ctrl)
	u64 temp;
	char *mode;

	if (ctrl->core_clk) {
		rc = clk_set_rate(ctrl->core_clk, ctrl->cpr_clock_rate);
		if (rc) {
			cpr3_err(ctrl, "clk_set_rate(core_clk, %u) failed, rc=%d\n",
				ctrl->cpr_clock_rate, rc);
			return rc;
		}
	}

	rc = cpr3_clock_enable(ctrl);
	if (rc) {
@@ -4332,9 +4334,6 @@ static int cpr3_regulator_validate_controller(struct cpr3_controller *ctrl)
	if (!ctrl->vdd_regulator) {
		cpr3_err(ctrl, "vdd regulator missing\n");
		return -EINVAL;
	} else if (!ctrl->core_clk) {
		cpr3_err(ctrl, "core clock missing\n");
		return -EINVAL;
	} else if (ctrl->sensor_count <= 0
		   || ctrl->sensor_count > CPR3_MAX_SENSOR_COUNT) {
		cpr3_err(ctrl, "invalid CPR sensor count=%d\n",
+8 −6
Original line number Diff line number Diff line
@@ -942,6 +942,7 @@ int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl)
		return rc;
	}

	if (of_find_property(ctrl->dev->of_node, "clock-names", NULL)) {
		ctrl->core_clk = devm_clk_get(ctrl->dev, "core_clk");
		if (IS_ERR(ctrl->core_clk)) {
			rc = PTR_ERR(ctrl->core_clk);
@@ -950,6 +951,7 @@ int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl)
				rc);
			return rc;
		}
	}

	ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev,
								"system");