Commit 3c7826d2 authored Mar 16, 2016 by Mayank Rana

usb: qmp: phy: Make sure QMP PHY reset write is completed



Add explicit memory barrier after programming USB3_PHY_SW_RESET
register which makes sure that above write is not cached. If
this register write is cached, then phy driver is timing out
with checking PCS status. In some cases, L2 cache memory error
is seen when that register write is flushed whereas usb phy
clock is turned off.

Change-Id: Iebe8cb4034721e76fa5ea63e33304b9dc0243797
Signed-off-by: Mayank Rana <mrana@codeaurora.org>

parent 8007444c

drivers/usb/phy/phy-msm-ssusb-qmp.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -614,6 +614,8 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy)
		writel_relaxed(0x03, phy->base + phy->phy_reg[USB3_PHY_START]);
		writel_relaxed(0x00, phy->base + phy->phy_reg[USB3_PHY_SW_RESET]);

		/* Make sure above write completed to bring PHY out of reset */
		mb();

		/* Wait for PHY initialization to be done */
		do {