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Commit 3c36cc68 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Liam Girdwood
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ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default 



It seams at least on twl5031 that the ARXR2_APGA_CTL register
does not have the same default value as it is written in
the TRM.
Since the codec part of the PM chip has not been actually
changed according to TI, assuming, that all version has
the same problem, so writing there the TRM value.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarLiam Girdwood <lrg@slimlogic.co.uk>
parent 9fdcc0f7

sound/soc/codecs/twl4030.c

+3 −0
Original line number Diff line number Diff line
@@ -289,6 +289,9 @@ static void twl4030_init_chip(struct platform_device *pdev) 
		TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |

		TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);



	/* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */

	twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);



	/* Machine dependent setup */

	if (!setup)

		return;