MIPS: Use WSBH/DSBH/DSHD on Loongson 3A (3c09bae4) · Commits · e / devices / android_kernel_xiaomi_markw

arch/mips/include/asm/cpu-features.h

+10 −0

Original line number	Original line	Diff line number	Diff line
	@@ -231,6 +231,16 @@
	#define cpu_has_clo_clz cpu_has_mips_r		#define cpu_has_clo_clz cpu_has_mips_r
	#endif		#endif

			/*
			* MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
			* MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
			* This indicates the availability of WSBH and in case of 64 bit CPUs also
			* DSBH and DSHD.
			*/
			#ifndef cpu_has_wsbh
			#define cpu_has_wsbh cpu_has_mips_r2
			#endif

	#ifndef cpu_has_dsp		#ifndef cpu_has_dsp
	#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)		#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
	#endif		#endif

arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -57,6 +57,7 @@
	#define cpu_has_vint 0		#define cpu_has_vint 0
	#define cpu_has_veic 0		#define cpu_has_veic 0
	#define cpu_hwrena_impl_bits 0xc0000000		#define cpu_hwrena_impl_bits 0xc0000000
			#define cpu_has_wsbh 1

	#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)		#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)

arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -59,4 +59,6 @@
	#define cpu_has_watch 1		#define cpu_has_watch 1
	#define cpu_has_local_ebase 0		#define cpu_has_local_ebase 0

			#define cpu_has_wsbh IS_ENABLED(CONFIG_CPU_LOONGSON3)

	#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */		#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/uapi/asm/swab.h

+14 −4

Original line number	Original line	Diff line number	Diff line
	@@ -13,12 +13,16 @@

	#define __SWAB_64_THRU_32__		#define __SWAB_64_THRU_32__

	#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)		#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \|\| \
			defined(_MIPS_ARCH_LOONGSON3A)

	static inline __attribute_const__ __u16 __arch_swab16(__u16 x)		static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
	{		{
	__asm__(		__asm__(
			" .set push \n"
			" .set arch=mips32r2 \n"
	" wsbh %0, %1 \n"		" wsbh %0, %1 \n"
			" .set pop \n"
	: "=r" (x)		: "=r" (x)
	: "r" (x));		: "r" (x));

	@@ -29,8 +33,11 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
	static inline __attribute_const__ __u32 __arch_swab32(__u32 x)		static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
	{		{
	__asm__(		__asm__(
			" .set push \n"
			" .set arch=mips32r2 \n"
	" wsbh %0, %1 \n"		" wsbh %0, %1 \n"
	" rotr %0, %0, 16 \n"		" rotr %0, %0, 16 \n"
			" .set pop \n"
	: "=r" (x)		: "=r" (x)
	: "r" (x));		: "r" (x));

	@@ -46,8 +53,11 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
	static inline __attribute_const__ __u64 __arch_swab64(__u64 x)		static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
	{		{
	__asm__(		__asm__(
			" .set push \n"
			" .set arch=mips64r2 \n"
	" dsbh %0, %1 \n"		" dsbh %0, %1 \n"
	" dshd %0, %0"		" dshd %0, %0 \n"
			" .set pop \n"
	: "=r" (x)		: "=r" (x)
	: "r" (x));		: "r" (x));

	@@ -55,5 +65,5 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
	}		}
	#define __arch_swab64 __arch_swab64		#define __arch_swab64 __arch_swab64
	#endif /* __mips64 */		#endif /* __mips64 */
	#endif /* MIPS R2 or newer */		#endif /* MIPS R2 or newer or Loongson 3A */
	#endif /* _ASM_SWAB_H */		#endif /* _ASM_SWAB_H */

arch/mips/lib/csum_partial.S

+8 −2

Original line number	Original line	Diff line number	Diff line
	@@ -277,9 +277,12 @@ LEAF(csum_partial)
	#endif		#endif

	/* odd buffer alignment? */		/* odd buffer alignment? */
	#ifdef CONFIG_CPU_MIPSR2		#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_LOONGSON3)
			.set push
			.set arch=mips32r2
	wsbh v1, sum		wsbh v1, sum
	movn sum, v1, t7		movn sum, v1, t7
			.set pop
	#else		#else
	beqz t7, 1f /* odd buffer alignment? */		beqz t7, 1f /* odd buffer alignment? */
	lui v1, 0x00ff		lui v1, 0x00ff
	@@ -726,9 +729,12 @@ LEAF(csum_partial)
	addu sum, v1		addu sum, v1
	#endif		#endif

	#ifdef CONFIG_CPU_MIPSR2		#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_LOONGSON3)
			.set push
			.set arch=mips32r2
	wsbh v1, sum		wsbh v1, sum
	movn sum, v1, odd		movn sum, v1, odd
			.set pop
	#else		#else
	beqz odd, 1f /* odd buffer alignment? */		beqz odd, 1f /* odd buffer alignment? */
	lui v1, 0x00ff		lui v1, 0x00ff