Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3b3a8001 authored by Sebastian Andrzej Siewior's avatar Sebastian Andrzej Siewior Committed by Mark Brown
Browse files

spi: ti-qspi: one only one interrupt handler 



The here used irq and threaded irq handler is a complete non-sense. After
the status register is read and the source disabled it schedules a thread
(the irq thread) to read the status from the variable, invoke complete()
and then renable the interrupt. Again: schedule a thread which invokes
_only_ complete().
This patch removes this non-sense and we remain with one handler which
invokes complete() if needed.
The device remove path should now disable the interupts.
This has been compile time tested.

Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Tested-by: default avatarSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 633795b9

drivers/spi/spi-ti-qspi.c

+6 −33
Original line number Diff line number Diff line
@@ -41,9 +41,6 @@ struct ti_qspi_regs { 
struct ti_qspi {

	struct completion       transfer_complete;



	/* IRQ synchronization */

	spinlock_t              lock;



	/* list synchronization */

	struct mutex            list_lock;
@@ -57,7 +54,6 @@ struct ti_qspi { 
	u32 spi_max_frequency;

	u32 cmd;

	u32 dc;

	u32 stat;

};



#define QSPI_PID			(0x0)
@@ -397,13 +393,12 @@ static irqreturn_t ti_qspi_isr(int irq, void *dev_id) 
{

	struct ti_qspi *qspi = dev_id;

	u16 int_stat;

	u32 stat;



	irqreturn_t ret = IRQ_HANDLED;



	spin_lock(&qspi->lock);



	int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);

	qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);

	stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);



	if (!int_stat) {

		dev_dbg(qspi->dev, "No IRQ triggered\n");
@@ -411,35 +406,14 @@ static irqreturn_t ti_qspi_isr(int irq, void *dev_id) 
		goto out;

	}



	ret = IRQ_WAKE_THREAD;



	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);

	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,

				QSPI_INTR_STATUS_ENABLED_CLEAR);



	if (stat & WC)

		complete(&qspi->transfer_complete);

out:

	spin_unlock(&qspi->lock);



	return ret;

}



static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)

{

	struct ti_qspi *qspi = dev_id;

	unsigned long flags;



	spin_lock_irqsave(&qspi->lock, flags);



	if (qspi->stat & WC)

		complete(&qspi->transfer_complete);



	spin_unlock_irqrestore(&qspi->lock, flags);



	ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);



	return IRQ_HANDLED;

}



static int ti_qspi_runtime_resume(struct device *dev)

{

	struct ti_qspi      *qspi;
@@ -499,7 +473,6 @@ static int ti_qspi_probe(struct platform_device *pdev) 
		return irq;

	}



	spin_lock_init(&qspi->lock);

	mutex_init(&qspi->list_lock);



	qspi->base = devm_ioremap_resource(&pdev->dev, r);
@@ -508,8 +481,7 @@ static int ti_qspi_probe(struct platform_device *pdev) 
		goto free_master;

	}



	ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr,

			ti_qspi_threaded_isr, 0,

	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,

			dev_name(&pdev->dev), qspi);

	if (ret < 0) {

		dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
@@ -547,6 +519,7 @@ static int ti_qspi_remove(struct platform_device *pdev) 
{

	struct	ti_qspi *qspi = platform_get_drvdata(pdev);



	ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);

	spi_unregister_master(qspi->master);



	return 0;