Commit 3ac78313 authored Oct 25, 2012 by Jesse Barnes Committed by Daniel Vetter Nov 11, 2012

drm/i915: PIPE_CONTROL TLB invalidate requires CS stall



"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 9a289771

drivers/gpu/drm/i915/intel_ringbuffer.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -245,7 +245,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
		/*
		* TLB invalidate requires a post-sync write.
		*/
		flags \|= PIPE_CONTROL_QW_WRITE;
		flags \|= PIPE_CONTROL_QW_WRITE \| PIPE_CONTROL_CS_STALL;
		}

		ret = intel_ring_begin(ring, 4);