Loading drivers/media/platform/msm/camera_v2/sensor/cci/msm_cci.c +12 −1 Original line number Diff line number Diff line Loading @@ -1190,7 +1190,7 @@ static int32_t msm_cci_init(struct v4l2_subdev *sd, uint8_t i = 0; int32_t rc = 0, ret = 0; struct cci_device *cci_dev; enum cci_i2c_master_t master; enum cci_i2c_master_t master = MASTER_0; struct msm_cam_clk_info *clk_info = NULL; cci_dev = v4l2_get_subdevdata(sd); Loading @@ -1207,6 +1207,12 @@ static int32_t msm_cci_init(struct v4l2_subdev *sd, if (master < MASTER_MAX && master >= 0) { mutex_lock(&cci_dev->cci_master_info[master].mutex); flush_workqueue(cci_dev->write_wq[master]); /* Re-initialize the completion */ reinit_completion(&cci_dev-> cci_master_info[master].reset_complete); for (i = 0; i < NUM_QUEUES; i++) reinit_completion(&cci_dev-> cci_master_info[master].report_q[i]); /* Set reset pending flag to TRUE */ cci_dev->cci_master_info[master].reset_pending = TRUE; /* Set proper mask to RESET CMD address */ Loading Loading @@ -1276,6 +1282,11 @@ static int32_t msm_cci_init(struct v4l2_subdev *sd, CDBG("%s: clk enable failed\n", __func__); goto reg_enable_failed; } /* Re-initialize the completion */ reinit_completion(&cci_dev->cci_master_info[master].reset_complete); for (i = 0; i < NUM_QUEUES; i++) reinit_completion(&cci_dev->cci_master_info[master]. report_q[i]); enable_irq(cci_dev->irq->start); cci_dev->hw_version = msm_camera_io_r_mb(cci_dev->base + CCI_HW_VERSION_ADDR); Loading Loading
drivers/media/platform/msm/camera_v2/sensor/cci/msm_cci.c +12 −1 Original line number Diff line number Diff line Loading @@ -1190,7 +1190,7 @@ static int32_t msm_cci_init(struct v4l2_subdev *sd, uint8_t i = 0; int32_t rc = 0, ret = 0; struct cci_device *cci_dev; enum cci_i2c_master_t master; enum cci_i2c_master_t master = MASTER_0; struct msm_cam_clk_info *clk_info = NULL; cci_dev = v4l2_get_subdevdata(sd); Loading @@ -1207,6 +1207,12 @@ static int32_t msm_cci_init(struct v4l2_subdev *sd, if (master < MASTER_MAX && master >= 0) { mutex_lock(&cci_dev->cci_master_info[master].mutex); flush_workqueue(cci_dev->write_wq[master]); /* Re-initialize the completion */ reinit_completion(&cci_dev-> cci_master_info[master].reset_complete); for (i = 0; i < NUM_QUEUES; i++) reinit_completion(&cci_dev-> cci_master_info[master].report_q[i]); /* Set reset pending flag to TRUE */ cci_dev->cci_master_info[master].reset_pending = TRUE; /* Set proper mask to RESET CMD address */ Loading Loading @@ -1276,6 +1282,11 @@ static int32_t msm_cci_init(struct v4l2_subdev *sd, CDBG("%s: clk enable failed\n", __func__); goto reg_enable_failed; } /* Re-initialize the completion */ reinit_completion(&cci_dev->cci_master_info[master].reset_complete); for (i = 0; i < NUM_QUEUES; i++) reinit_completion(&cci_dev->cci_master_info[master]. report_q[i]); enable_irq(cci_dev->irq->start); cci_dev->hw_version = msm_camera_io_r_mb(cci_dev->base + CCI_HW_VERSION_ADDR); Loading