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Commit 39ef0c6b authored by Rama Krishna Phani A's avatar Rama Krishna Phani A Committed by Gerrit - the friendly Code Review server
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msm: ep_pcie: Update aggregate IRQ logic 



Some targets support individual interrupt line for MHI a7
and MHI driver can register for interrupt handler. Avoid
programming MHI a7 interrupt bit from PCIe in such case.

Change-Id: I5aeb136d087ac2daadbddff5c41849e13aec9329
Signed-off-by: default avatarRama Krishna Phani A <rphani@codeaurora.org>
parent 83f78506

Documentation/devicetree/bindings/pci/msm_ep_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ Optional Properties: 
  - qcom,pcie-active-config: boolean type; active configuration of PCIe

    addressing.

  - qcom,pcie-aggregated-irq: boolean type; interrupts are aggregated.

  - qcom,pcie-mhi-a7-irq: boolean type; MHI a7 has separate irq.

  - qcom,pcie-perst-enum: Link enumeration will be triggered by PERST

    deassertion.

  - mdm2apstatus-gpio: GPIO used by PCIe endpoint side to notify the host side.
@@ -117,6 +118,7 @@ Example: 
		qcom,pcie-link-speed = <1>;

		qcom,pcie-active-config;

		qcom,pcie-aggregated-irq;

		qcom,pcie-mhi-a7-irq;

		qcom,pcie-perst-enum;

		qcom,phy-status-reg = <0x728>;

		qcom,dbi-base-reg = <0x168>;

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −0
Original line number Diff line number Diff line
@@ -289,6 +289,7 @@ struct ep_pcie_dev_t { 
	u32                          link_speed;

	bool                         active_config;

	bool                         aggregated_irq;

	bool                         mhi_a7_irq;

	u32                          dbi_base_reg;

	u32                          slv_space_reg;

	u32                          phy_status_reg;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+12 −1
Original line number Diff line number Diff line
@@ -600,9 +600,13 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
			BIT(EP_PCIE_INT_EVT_LINK_DOWN) |

			BIT(EP_PCIE_INT_EVT_BME) |

			BIT(EP_PCIE_INT_EVT_PM_TURNOFF) |

			BIT(EP_PCIE_INT_EVT_MHI_A7) |

			BIT(EP_PCIE_INT_EVT_DSTATE_CHANGE) |

			BIT(EP_PCIE_INT_EVT_LINK_UP));

		if (!dev->mhi_a7_irq)

			ep_pcie_write_mask(dev->parf +

				PCIE20_PARF_INT_ALL_MASK, 0,

				BIT(EP_PCIE_INT_EVT_MHI_A7));



		EP_PCIE_DBG(dev, "PCIe V%d: PCIE20_PARF_INT_ALL_MASK:0x%x\n",

			dev->rev,

			readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK));
@@ -2287,6 +2291,13 @@ static int ep_pcie_probe(struct platform_device *pdev) 
		"PCIe V%d: aggregated IRQ is %s enabled.\n",

		ep_pcie_dev.rev, ep_pcie_dev.aggregated_irq ? "" : "not");



	ep_pcie_dev.mhi_a7_irq =

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,pcie-mhi-a7-irq");

	EP_PCIE_DBG(&ep_pcie_dev,

		"PCIe V%d: Mhi a7 IRQ is %s enabled.\n",

		ep_pcie_dev.rev, ep_pcie_dev.mhi_a7_irq ? "" : "not");



	ep_pcie_dev.perst_enum = of_property_read_bool((&pdev->dev)->of_node,

				"qcom,pcie-perst-enum");

	EP_PCIE_DBG(&ep_pcie_dev,