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Commit 39cca10d authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

msm: kgsl: Make use of ADRENO_CONTENT_PROTECTION flag



A5x GPU comes up in secure mode by default but sometimes it
doesn't support content protection and corresponding
secure microcode. GPU cannot be moved to unsecure
mode without secure microcode.

Insert PM4 commands to move the GPU from secure to
unsecure only if it has ADRENO_CONTENT_PROTECTION feature
otherwise fallback to CPU and reset the register
A5XX_RBBM_SECVID_TRUST_CNTL.

Change-Id: I8c4ac26f3ef2b87a46bb2d171d2be6af75425d67
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent aa3aa09a
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+0 −2
Original line number Diff line number Diff line
@@ -678,8 +678,6 @@ struct adreno_gpudev {
	void (*init)(struct adreno_device *);
	int (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *);
	int (*hw_init)(struct adreno_device *);
	int (*switch_to_unsecure_mode)(struct adreno_device *,
				struct adreno_ringbuffer *);
	int (*microcode_read)(struct adreno_device *);
	int (*microcode_load)(struct adreno_device *, unsigned int start_type);
	void (*perfcounter_init)(struct adreno_device *);
+34 −26
Original line number Diff line number Diff line
@@ -1866,6 +1866,11 @@ static void a5xx_post_start(struct adreno_device *adreno_dev)
static int a5xx_hw_init(struct adreno_device *adreno_dev)
{
	int ret;
	struct kgsl_device *device = &adreno_dev->dev;

	/* GPU comes up in secured mode, make it unsecured by default */
	if (!ADRENO_FEATURE(adreno_dev, ADRENO_CONTENT_PROTECTION))
		kgsl_regwrite(device, A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);

	/* Set up LM before initializing the GPMU */
	a5xx_lm_init(adreno_dev);
@@ -1886,6 +1891,32 @@ static int a5xx_hw_init(struct adreno_device *adreno_dev)
	return 0;
}

static int a5xx_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
				struct adreno_ringbuffer *rb)
{
	unsigned int *cmds;
	int ret;

	cmds = adreno_ringbuffer_allocspace(rb, 2);
	if (IS_ERR(cmds))
		return PTR_ERR(cmds);
	if (cmds == NULL)
		return -ENOSPC;

	cmds += cp_secure_mode(adreno_dev, cmds, 0);

	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
	if (ret != 0) {
		struct kgsl_device *device = &adreno_dev->dev;

		dev_err(device->dev, "Switch to unsecure failed to idle\n");
		spin_idle_debug(device);
		kgsl_device_snapshot(device, NULL);
	}

	return ret;
}

/*
 * a5xx_rb_init() - Initialize ringbuffer
 * @adreno_dev: Pointer to adreno device
@@ -1936,31 +1967,9 @@ static int a5xx_rb_init(struct adreno_device *adreno_dev,
		kgsl_device_snapshot(device, NULL);
	}

	return ret;
}

int a5xx_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
				struct adreno_ringbuffer *rb)
{
	unsigned int *cmds;
	int ret;

	cmds = adreno_ringbuffer_allocspace(rb, 2);
	if (IS_ERR(cmds))
		return PTR_ERR(cmds);
	if (cmds == NULL)
		return -ENOSPC;

	cmds += cp_secure_mode(adreno_dev, cmds, 0);

	ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
	if (ret != 0) {
		struct kgsl_device *device = &adreno_dev->dev;

		dev_err(device->dev, "Switch to unsecure failed to idle\n");
		spin_idle_debug(device);
		kgsl_device_snapshot(device, NULL);
	}
	/* GPU comes up in secured mode, make it unsecured by default */
	if (ADRENO_FEATURE(adreno_dev, ADRENO_CONTENT_PROTECTION))
		ret = a5xx_switch_to_unsecure_mode(adreno_dev, rb);

	return ret;
}
@@ -3377,7 +3386,6 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
	.init = a5xx_init,
	.rb_init = a5xx_rb_init,
	.hw_init = a5xx_hw_init,
	.switch_to_unsecure_mode = a5xx_switch_to_unsecure_mode,
	.microcode_read = a5xx_microcode_read,
	.microcode_load = a5xx_microcode_load,
	.perfcounters = &a5xx_perfcounters,
+0 −3
Original line number Diff line number Diff line
@@ -334,9 +334,6 @@ static int _ringbuffer_start_common(struct adreno_ringbuffer *rb)
	if (status)
		return status;

	if (gpudev->switch_to_unsecure_mode)
		status = gpudev->switch_to_unsecure_mode(adreno_dev, rb);

	return status;
}