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Commit 39a51109 authored by Ralf Baechle's avatar Ralf Baechle
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[MIPS] Extend performance counter event field. 



The latest draft version of the MIPS Architecture Specification extends the
6 bit event field by adding a directly adjacent 4-bit EventExt field for a
total of 10 bits.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 231a35d3

arch/mips/oprofile/op_model_mipsxx.c

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)

#define M_PERFCTL_USER			(1UL      <<  3)

#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)

#define M_PERFCTL_EVENT(event)		(((event) & 0x3f)  << 5)

#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)

#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)

#define M_PERFCTL_MT_EN(filter)		((filter) << 20)

#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)