Loading drivers/gpu/msm/a5xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -637,6 +637,7 @@ #define A5XX_UCHE_GMEM_RANGE_MAX_LO 0xE8D #define A5XX_UCHE_GMEM_RANGE_MAX_HI 0xE8E #define A5XX_UCHE_INVALIDATE0 0xE95 #define A5XX_UCHE_CACHE_WAYS 0xE96 #define A5XX_UCHE_PERFCTR_UCHE_SEL_0 0xEA0 #define A5XX_UCHE_PERFCTR_UCHE_SEL_1 0xEA1 #define A5XX_UCHE_PERFCTR_UCHE_SEL_2 0xEA2 Loading drivers/gpu/msm/adreno_a5xx.c +6 −0 Original line number Diff line number Diff line Loading @@ -1350,6 +1350,12 @@ static void a5xx_start(struct adreno_device *adreno_dev) /* Turn on performance counters */ kgsl_regwrite(device, A5XX_RBBM_PERFCTR_CNTL, 0x01); /* * This is to increase performance by restricting VFD's cache access, * so that LRZ and other data get evicted less. */ kgsl_regwrite(device, A5XX_UCHE_CACHE_WAYS, 0x02); /* * Set UCHE_WRITE_THRU_BASE to the UCHE_TRAP_BASE effectively * disabling L2 bypass Loading Loading
drivers/gpu/msm/a5xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -637,6 +637,7 @@ #define A5XX_UCHE_GMEM_RANGE_MAX_LO 0xE8D #define A5XX_UCHE_GMEM_RANGE_MAX_HI 0xE8E #define A5XX_UCHE_INVALIDATE0 0xE95 #define A5XX_UCHE_CACHE_WAYS 0xE96 #define A5XX_UCHE_PERFCTR_UCHE_SEL_0 0xEA0 #define A5XX_UCHE_PERFCTR_UCHE_SEL_1 0xEA1 #define A5XX_UCHE_PERFCTR_UCHE_SEL_2 0xEA2 Loading
drivers/gpu/msm/adreno_a5xx.c +6 −0 Original line number Diff line number Diff line Loading @@ -1350,6 +1350,12 @@ static void a5xx_start(struct adreno_device *adreno_dev) /* Turn on performance counters */ kgsl_regwrite(device, A5XX_RBBM_PERFCTR_CNTL, 0x01); /* * This is to increase performance by restricting VFD's cache access, * so that LRZ and other data get evicted less. */ kgsl_regwrite(device, A5XX_UCHE_CACHE_WAYS, 0x02); /* * Set UCHE_WRITE_THRU_BASE to the UCHE_TRAP_BASE effectively * disabling L2 bypass Loading