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Commit 3863c9bc authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/instmem: completely new implementation, as a subdev module 



v2 (Ben Skeggs):
- some fixes for 64KiB PAGE_SIZE
- fix porting issues in (currently unused) nv41/nv44 pciegart code

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 8a9b889e

drivers/gpu/drm/nouveau/Makefile

+8 −1
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ ccflags-y += -I$(src) 
nouveau-y := core/core/client.o

nouveau-y += core/core/engine.o

nouveau-y += core/core/enum.o

nouveau-y += core/core/gpuobj.o

nouveau-y += core/core/handle.o

nouveau-y += core/core/mm.o

nouveau-y += core/core/namedb.o
@@ -19,6 +20,9 @@ nouveau-y += core/core/printk.o 
nouveau-y += core/core/ramht.o

nouveau-y += core/core/subdev.o



nouveau-y += core/subdev/bar/base.o

nouveau-y += core/subdev/bar/nv50.o

nouveau-y += core/subdev/bar/nvc0.o

nouveau-y += core/subdev/bios/base.o

nouveau-y += core/subdev/bios/bit.o

nouveau-y += core/subdev/bios/conn.o
@@ -66,10 +70,10 @@ nouveau-y += core/subdev/gpio/nvd0.o 
nouveau-y += core/subdev/i2c/base.o

nouveau-y += core/subdev/i2c/aux.o

nouveau-y += core/subdev/i2c/bit.o

nouveau-y += core/subdev/instmem/base.o

nouveau-y += core/subdev/instmem/nv04.o

nouveau-y += core/subdev/instmem/nv40.o

nouveau-y += core/subdev/instmem/nv50.o

nouveau-y += core/subdev/instmem/nvc0.o

nouveau-y += core/subdev/ltcg/nvc0.o

nouveau-y += core/subdev/mc/base.o

nouveau-y += core/subdev/mc/nv04.o
@@ -80,6 +84,9 @@ nouveau-y += core/subdev/mc/nvc0.o 
nouveau-y += core/subdev/timer/base.o

nouveau-y += core/subdev/timer/nv04.o

nouveau-y += core/subdev/vm/base.o

nouveau-y += core/subdev/vm/nv04.o

nouveau-y += core/subdev/vm/nv41.o

nouveau-y += core/subdev/vm/nv44.o

nouveau-y += core/subdev/vm/nv50.o

nouveau-y += core/subdev/vm/nvc0.o

drivers/gpu/drm/nouveau/core/core/ramht.c

+6 −9
Original line number Diff line number Diff line
@@ -86,7 +86,6 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle, 
{

	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;

	struct nouveau_ramht_entry *entry;

	struct nouveau_gpuobj *ramht = chan->ramht->gpuobj;

	unsigned long flags;
@@ -104,21 +103,21 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle, 
	nouveau_gpuobj_ref(gpuobj, &entry->gpuobj);



	if (dev_priv->card_type < NV_40) {

		ctx = NV_RAMHT_CONTEXT_VALID | (gpuobj->pinst >> 4) |

		ctx = NV_RAMHT_CONTEXT_VALID | (gpuobj->addr >> 4) |

		      (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |

		      (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);

	} else

	if (dev_priv->card_type < NV_50) {

		ctx = (gpuobj->pinst >> 4) |

		ctx = (gpuobj->addr >> 4) |

		      (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |

		      (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);

	} else {

		if (gpuobj->engine == NVOBJ_ENGINE_DISPLAY) {

			ctx = (gpuobj->cinst << 10) |

			ctx = (gpuobj->node->offset << 10) |

			      (chan->id << 28) |

			      chan->id; /* HASH_TAG */

		} else {

			ctx = (gpuobj->cinst >> 4) |

			ctx = (gpuobj->node->offset >> 4) |

			      ((gpuobj->engine <<

				NV40_RAMHT_CONTEXT_ENGINE_SHIFT));

		}
@@ -137,7 +136,7 @@ nouveau_ramht_insert(struct nouveau_channel *chan, u32 handle, 
			nv_wo32(ramht, co + 4, ctx);



			spin_unlock_irqrestore(&chan->ramht->lock, flags);

			instmem->flush(dev);

			nvimem_flush(dev);

			return 0;

		}

		NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
@@ -184,8 +183,6 @@ static void 
nouveau_ramht_remove_hash(struct nouveau_channel *chan, u32 handle)

{

	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;

	struct nouveau_gpuobj *ramht = chan->ramht->gpuobj;

	unsigned long flags;

	u32 co, ho;
@@ -201,7 +198,7 @@ nouveau_ramht_remove_hash(struct nouveau_channel *chan, u32 handle) 
				 chan->id, co, handle, nv_ro32(ramht, co + 4));

			nv_wo32(ramht, co + 0, 0x00000000);

			nv_wo32(ramht, co + 4, 0x00000000);

			instmem->flush(dev);

			nvimem_flush(dev);

			goto out;

		}

drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c

+0 −1
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ 
#include "drmP.h"

#include "nouveau_drv.h"

#include "nouveau_util.h"

#include <subdev/vm.h>

#include <core/ramht.h>



/*XXX: This stub is currently used on NV98+ also, as soon as this becomes

drivers/gpu/drm/nouveau/core/engine/copy/nva3.c

+5 −7
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#include "drmP.h"

#include "nouveau_drv.h"

#include "nouveau_util.h"

#include <subdev/vm.h>

#include <core/ramht.h>

#include "fuc/nva3.fuc.h"
@@ -38,7 +37,6 @@ static int 
nva3_copy_context_new(struct nouveau_channel *chan, int engine)

{

	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_gpuobj *ramin = chan->ramin;

	struct nouveau_gpuobj *ctx = NULL;

	int ret;
@@ -51,14 +49,14 @@ nva3_copy_context_new(struct nouveau_channel *chan, int engine) 
		return ret;



	nv_wo32(ramin, 0xc0, 0x00190000);

	nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1);

	nv_wo32(ramin, 0xc8, ctx->vinst);

	nv_wo32(ramin, 0xc4, ctx->addr + ctx->size - 1);

	nv_wo32(ramin, 0xc8, ctx->addr);

	nv_wo32(ramin, 0xcc, 0x00000000);

	nv_wo32(ramin, 0xd0, 0x00000000);

	nv_wo32(ramin, 0xd4, 0x00000000);

	dev_priv->engine.instmem.flush(dev);

	nvimem_flush(dev);



	atomic_inc(&chan->vm->engref[engine]);

	nvvm_engref(chan->vm, engine, 1);

	chan->engctx[engine] = ctx;

	return 0;

}
@@ -84,7 +82,7 @@ nva3_copy_context_del(struct nouveau_channel *chan, int engine) 
	for (i = 0xc0; i <= 0xd4; i += 4)

		nv_wo32(chan->ramin, i, 0x00000000);



	atomic_dec(&chan->vm->engref[engine]);

	nvvm_engref(chan->vm, engine, -1);

	nouveau_gpuobj_ref(NULL, &ctx);

	chan->engctx[engine] = ctx;

}

drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c

+3 −5
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#include "drmP.h"

#include "nouveau_drv.h"

#include "nouveau_util.h"

#include <subdev/vm.h>

#include <core/ramht.h>

#include "fuc/nvc0.fuc.h"
@@ -49,7 +48,6 @@ nvc0_copy_context_new(struct nouveau_channel *chan, int engine) 
	struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);

	struct nvc0_copy_chan *cctx;

	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_gpuobj *ramin = chan->ramin;

	int ret;
@@ -62,14 +60,14 @@ nvc0_copy_context_new(struct nouveau_channel *chan, int engine) 
	if (ret)

		return ret;



	ret = nouveau_gpuobj_map_vm(cctx->mem, NV_MEM_ACCESS_RW, chan->vm,

	ret = nouveau_gpuobj_map_vm(cctx->mem, chan->vm, NV_MEM_ACCESS_RW,

				   &cctx->vma);

	if (ret)

		return ret;



	nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(cctx->vma.offset));

	nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(cctx->vma.offset));

	dev_priv->engine.instmem.flush(dev);

	nvimem_flush(dev);

	return 0;

}
@@ -88,7 +86,7 @@ nvc0_copy_context_del(struct nouveau_channel *chan, int engine) 
	struct drm_device *dev = chan->dev;

	u32 inst;



	inst  = (chan->ramin->vinst >> 12);

	inst  = (chan->ramin->addr >> 12);

	inst |= 0x40000000;



	/* disable fifo access */