Commit 37cddff8 authored Jul 11, 2014 by Paul Burton Committed by Ralf Baechle Aug 02, 2014

MIPS: 16 byte align MSA vector context



The MSA specification upon first read appears to suggest that it is safe
to perform vector loads & stores with arbitrary alignment. However it
leaves provision for "address-dependent exceptions"... Align the vector
context to a 16 byte boundary to ensure that the kernel cannot cause any
such exceptions.

Note that the fpu field of struct thread_struct was already at a 16 byte
boundary within the struct, the introduction of FPU_ALIGN simply makes
the requirement explicit. The only part of this impacting the generated
kernel binary is ARCH_MIN_TASKALIGN.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7308/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 762a1f43

arch/mips/include/asm/processor.h

+8 −2

Original line number	Diff line number	Diff line
		@@ -238,7 +238,13 @@ typedef struct {
		unsigned long seg;
		} mm_segment_t;

		#ifdef CONFIG_CPU_HAS_MSA
		# define ARCH_MIN_TASKALIGN 16
		# define FPU_ALIGN __aligned(16)
		#else
		# define ARCH_MIN_TASKALIGN 8
		# define FPU_ALIGN
		#endif

		struct mips_abi;

		@@ -255,7 +261,7 @@ struct thread_struct {
		unsigned long cp0_status;

		/* Saved fpu/fpu emulator stuff. */
		struct mips_fpu_struct fpu;
		struct mips_fpu_struct fpu FPU_ALIGN;
		#ifdef CONFIG_MIPS_MT_FPAFF
		/* Emulated instruction count */
		unsigned long emulated_fp;