Loading Documentation/devicetree/bindings/gpu/adreno.txt +2 −1 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ Required properties: KGSL_CLK_MEM_IFACE 0x00000010 KGSL_CLK_AXI 0x00000020 KGSL_CLK_RBBMTIMER 0x00000080 KGSL_CLK_ALWAYSON 0x00000800 - clocks: List of phandle and clock specifier pairs, one pair for each clock input to the device. Loading @@ -30,7 +31,7 @@ Required properties: order as the clocks property. Current values of clock-names are: "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", "alt_mem_iface_clk", "rbbmtimer_clk" "alt_mem_iface_clk", "rbbmtimer_clk", "alwayson_clk" "core_clk" and "iface_clk" are required and others are optional - qcom,gpu-efuse-leakage: memory region for GPU power rail leakage. Loading drivers/gpu/msm/kgsl_pwrctrl.c +4 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,10 @@ static struct clk_pair clks[KGSL_MAX_CLKS] = { .name = "gtbu_clk", .map = KGSL_CLK_GFX_GTBU, }, { .name = "alwayson_clk", .map = KGSL_CLK_ALWAYSON, }, }; static struct clk_pair dummy_mx_clk = { Loading drivers/gpu/msm/kgsl_pwrctrl.h +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ #define KGSL_PWR_ON 0xFFFF #define KGSL_MAX_CLKS 9 #define KGSL_MAX_CLKS 10 #define KGSL_MAX_REGULATORS 2 #define KGSL_MAX_REGULATOR_NAME_LEN 8 Loading include/linux/msm_kgsl.h +1 −0 Original line number Diff line number Diff line Loading @@ -15,6 +15,7 @@ #define KGSL_CLK_GFX_GTCU 0x00000100 #define KGSL_CLK_GFX_GTBU 0x00000200 #define KGSL_CLK_MX 0x00000400 #define KGSL_CLK_ALWAYSON 0x00000800 #define KGSL_MAX_PWRLEVELS 10 Loading Loading
Documentation/devicetree/bindings/gpu/adreno.txt +2 −1 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ Required properties: KGSL_CLK_MEM_IFACE 0x00000010 KGSL_CLK_AXI 0x00000020 KGSL_CLK_RBBMTIMER 0x00000080 KGSL_CLK_ALWAYSON 0x00000800 - clocks: List of phandle and clock specifier pairs, one pair for each clock input to the device. Loading @@ -30,7 +31,7 @@ Required properties: order as the clocks property. Current values of clock-names are: "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", "alt_mem_iface_clk", "rbbmtimer_clk" "alt_mem_iface_clk", "rbbmtimer_clk", "alwayson_clk" "core_clk" and "iface_clk" are required and others are optional - qcom,gpu-efuse-leakage: memory region for GPU power rail leakage. Loading
drivers/gpu/msm/kgsl_pwrctrl.c +4 −0 Original line number Diff line number Diff line Loading @@ -96,6 +96,10 @@ static struct clk_pair clks[KGSL_MAX_CLKS] = { .name = "gtbu_clk", .map = KGSL_CLK_GFX_GTBU, }, { .name = "alwayson_clk", .map = KGSL_CLK_ALWAYSON, }, }; static struct clk_pair dummy_mx_clk = { Loading
drivers/gpu/msm/kgsl_pwrctrl.h +1 −1 Original line number Diff line number Diff line Loading @@ -25,7 +25,7 @@ #define KGSL_PWR_ON 0xFFFF #define KGSL_MAX_CLKS 9 #define KGSL_MAX_CLKS 10 #define KGSL_MAX_REGULATORS 2 #define KGSL_MAX_REGULATOR_NAME_LEN 8 Loading
include/linux/msm_kgsl.h +1 −0 Original line number Diff line number Diff line Loading @@ -15,6 +15,7 @@ #define KGSL_CLK_GFX_GTCU 0x00000100 #define KGSL_CLK_GFX_GTBU 0x00000200 #define KGSL_CLK_MX 0x00000400 #define KGSL_CLK_ALWAYSON 0x00000800 #define KGSL_MAX_PWRLEVELS 10 Loading