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Commit 35d110e7 authored by Kevin Liu's avatar Kevin Liu Committed by Chris Ball
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mmc: sdhci-pxav3: Add base clock quirk 



Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since
SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base clock value.
It returns a fixed pre-set value like 200 on some sdhci-pxav3 based
platforms like MMP3 while return 0 on the other sdhci-pxav3 based
platforms.  So we enable the quirk and get the base clock via function
get_max_clock. Also add get_max_clock.

Reported-by: default avatarPhilip Rakity <prakity@marvell.com>
Reviewed-by: default avatarPhilip Rakity <prakity@Marvell.com>
Acked-by: default avatarZhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: default avatarKevin Liu <kliu5@marvell.com>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent 5f1a4dd0

drivers/mmc/host/sdhci-pxav3.c

+10 −1
Original line number Diff line number Diff line
@@ -163,10 +163,18 @@ static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 
	return 0;

}



static u32 pxav3_get_max_clock(struct sdhci_host *host)

{

	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);



	return clk_get_rate(pltfm_host->clk);

}



static struct sdhci_ops pxav3_sdhci_ops = {

	.platform_reset_exit = pxav3_set_private_registers,

	.set_uhs_signaling = pxav3_set_uhs_signaling,

	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,

	.get_max_clock = pxav3_get_max_clock,

};



#ifdef CONFIG_OF
@@ -249,7 +257,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev) 


	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL

		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC

		| SDHCI_QUIRK_32BIT_ADMA_SIZE;

		| SDHCI_QUIRK_32BIT_ADMA_SIZE

		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;



	/* enable 1/8V DDR capable */

	host->mmc->caps |= MMC_CAP_1_8V_DDR;