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Commit 346874c9 authored by Nadav Amit's avatar Nadav Amit Committed by Marcelo Tosatti
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KVM: x86: Fix CR3 reserved bits 



According to Intel specifications, PAE and non-PAE does not have any reserved
bits.  In long-mode, regardless to PCIDE, only the high bits (above the
physical address) are reserved.

Signed-off-by: default avatarNadav Amit <namit@cs.technion.ac.il>
Signed-off-by: default avatarMarcelo Tosatti <mtosatti@redhat.com>
parent 671bd993

arch/x86/include/asm/kvm_host.h

+1 −5
Original line number Diff line number Diff line
@@ -50,11 +50,7 @@ 
			  | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \

			  | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))



#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)

#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))

#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL

#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |	\

				  0xFFFFFF0000000000ULL)

#define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL

#define CR4_RESERVED_BITS                                               \

	(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\

			  | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \

arch/x86/kvm/emulate.c

+0 −4
Original line number Diff line number Diff line
@@ -3388,10 +3388,6 @@ static int check_cr_write(struct x86_emulate_ctxt *ctxt) 
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);

		if (efer & EFER_LMA)

			rsvd = CR3_L_MODE_RESERVED_BITS;

		else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)

			rsvd = CR3_PAE_RESERVED_BITS;

		else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)

			rsvd = CR3_NONPAE_RESERVED_BITS;



		if (new_val & rsvd)

			return emulate_gp(ctxt, 0);

arch/x86/kvm/x86.c

+5 −20
Original line number Diff line number Diff line
@@ -701,26 +701,11 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 
		return 0;

	}



	if (is_long_mode(vcpu)) {

		if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {

			if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)

				return 1;

		} else

			if (cr3 & CR3_L_MODE_RESERVED_BITS)

				return 1;

	} else {

		if (is_pae(vcpu)) {

			if (cr3 & CR3_PAE_RESERVED_BITS)

	if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS))

		return 1;

			if (is_paging(vcpu) &&

	if (is_pae(vcpu) && is_paging(vcpu) &&

	    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))

		return 1;

		}

		/*

		 * We don't check reserved bits in nonpae mode, because

		 * this isn't enforced, and VMware depends on this.

		 */

	}



	vcpu->arch.cr3 = cr3;

	__set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);