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Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by:Haiying Wang <Haiying.Wang@freescale.com> Acked-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>