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Commit 340cba60 authored by Jingoo Han's avatar Jingoo Han Committed by Arnd Bergmann
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pci: Add PCIe driver for Samsung Exynos 



Exynos5440 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.

Signed-off-by: default avatarSurendranath Gurivireddy Balla <suren.reddy@samsung.com>
Signed-off-by: default avatarSiva Reddy Kallam <siva.kallam@samsung.com>
Signed-off-by: default avatarJingoo Han <jg1.han@samsung.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent ece585df

Documentation/devicetree/bindings/pci/designware-pcie.txt

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* Synopsis Designware PCIe interface



Required properties:

- compatible: should contain "snps,dw-pcie" to identify the

	core, plus an identifier for the specific instance, such

	as "samsung,exynos5440-pcie".

- reg: base addresses and lengths of the pcie controller,

	the phy controller, additional register for the phy controller.

- interrupts: interrupt values for level interrupt,

	pulse interrupt, special interrupt.

- clocks: from common clock binding: handle to pci clock.

- clock-names: from common clock binding: should be "pcie" and "pcie_bus".

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"

- ranges: ranges for the PCI memory and I/O regions

- #interrupt-cells: set to <1>

- interrupt-map-mask and interrupt-map: standard PCI properties

	to define the mapping of the PCIe interface to interrupt

	numbers.

- reset-gpio: gpio pin number of power good signal



Example:



SoC specific DT Entry:



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000

			0x270000 0x1000

			0x271000 0x40>;

		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0x0 0 &gic 53>;

	};



	pcie@2a0000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x2a0000 0x1000

			0x272000 0x1000

			0x271040 0x40>;

		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;

		clocks = <&clock 29>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0x0 0 &gic 56>;

	};



Board specific DT Entry:



	pcie@290000 {

		reset-gpio = <&pin_ctrl 5 0>;

	};



	pcie@2a0000 {

		reset-gpio = <&pin_ctrl 22 0>;

	};

drivers/pci/host/Kconfig

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@@ -5,4 +5,13 @@ config PCI_MVEBU 
	bool "Marvell EBU PCIe controller"

	depends on ARCH_MVEBU || ARCH_KIRKWOOD



config PCIE_DW

	bool



config PCI_EXYNOS

	bool "Samsung Exynos PCIe controller"

	depends on SOC_EXYNOS5440

	select PCIEPORTBUS

	select PCIE_DW



endmenu

drivers/pci/host/Makefile

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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o

obj-$(CONFIG_PCIE_DW) += pcie-designware.o

drivers/pci/host/pcie-designware.c

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File added.

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