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Commit 32c50570 authored by Jaydeep Sen's avatar Jaydeep Sen
Browse files

clk: msm: mdmfermium: Correct voting levels for a7sspll in mdmfermium 



Voting level for a7sspll will be as per the stromer PLL specifictions.
Correct it to reflect the same.

Change-Id: I0a81a07ba9d05f65f4350c185d1b917c1b513452
Signed-off-by: default avatarJaydeep Sen <jsen@codeaurora.org>
parent 95314eae

drivers/clk/msm/clock-gcc-mdmfermium.c

+1 −2
Original line number Diff line number Diff line
@@ -113,8 +113,7 @@ static struct alpha_pll_clk a7sspll = { 
		.parent = &xo_a_clk_src.c,

		.dbg_name = "a7sspll",

		.ops = &clk_ops_dyna_alpha_pll,

		VDD_STROMER_FMAX_MAP3(LOWER, 400000000, NOMINAL, 800000000,

					HIGH, 1200000000),

		VDD_STROMER_FMAX_MAP1(LOW, 140000000),

		CLK_INIT(a7sspll.c),

	},

};

include/dt-bindings/clock/mdm-clocks-hwio-fermium.h

+1 −3
Original line number Diff line number Diff line
@@ -196,12 +196,10 @@ static int vdd_corner[] = { 
static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);





#define VDD_STROMER_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \

#define VDD_STROMER_FMAX_MAP1(l1, f1) \

	.vdd_class = &vdd_stromer_pll, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

		[VDD_DIG_##l2] = (f2),          \

		[VDD_DIG_##l3] = (f3),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM