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Commit 32bf87e3 authored by Andres Salomon's avatar Andres Salomon Committed by Linus Torvalds
Browse files

x86: geode: MSR cleanup 



This cleans up a few MSR-using drivers in the following manner:
  - Ensures MSRs are all defined in asm/geode.h, rather than in misc
    places
  - Makes the naming consistent; cs553[56] ones begin with MSR_,
    GX-specific ones start with MSR_GX_, and LX-specific ones start
    with MSR_LX_.  Also, make the names match the data sheet.
  - Use MSR names rather than numbers in source code
  - Document the fact that the LX's MSR_PADSEL has the wrong value
    in the data sheet.  That's, uh, good to note.

Signed-off-by: default avatarAndres Salomon <dilinger@debian.org>
Acked-by: default avatarJordan Crouse <jordan.crouse@amd.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 22af89aa

arch/x86/kernel/mfgpt_32.c

+4 −4
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ static int __init mfgpt_fix(char *s) 


	/* The following udocumented bit resets the MFGPT timers */

	val = 0xFF; dummy = 0;

	wrmsr(0x5140002B, val, dummy);

	wrmsr(MSR_MFGPT_SETUP, val, dummy);

	return 1;

}

__setup("mfgptfix", mfgpt_fix);
@@ -127,17 +127,17 @@ int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable) 
		 * 6; that is, resets for 7 and 8 will be ignored.  Is this

		 * a problem?   -dilinger

		 */

		msr = MFGPT_NR_MSR;

		msr = MSR_MFGPT_NR;

		mask = 1 << (timer + 24);

		break;



	case MFGPT_EVENT_NMI:

		msr = MFGPT_NR_MSR;

		msr = MSR_MFGPT_NR;

		mask = 1 << (timer + shift);

		break;



	case MFGPT_EVENT_IRQ:

		msr = MFGPT_IRQ_MSR;

		msr = MSR_MFGPT_IRQ;

		mask = 1 << (timer + shift);

		break;

drivers/video/geode/display_gx.h

+0 −1
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ int gx_line_delta(int xres, int bpp); 
extern struct geode_dc_ops gx_dc_ops;



/* MSR that tells us if a TFT or CRT is attached */

#define GLD_MSR_CONFIG   0xC0002001

#define GLD_MSR_CONFIG_DM_FP 0x40



/* Display controller registers */

drivers/video/geode/gxfb_core.c

+2 −1
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include <linux/fb.h>

#include <linux/init.h>

#include <linux/pci.h>

#include <asm/geode.h>



#include "geodefb.h"

#include "display_gx.h"
@@ -326,7 +327,7 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i 


	/* Figure out if this is a TFT or CRT part */



	rdmsrl(GLD_MSR_CONFIG, val);

	rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);



	if ((val & GLD_MSR_CONFIG_DM_FP) == GLD_MSR_CONFIG_DM_FP)

		par->enable_crt = 0;

drivers/video/geode/lxfb.h

+0 −8
Original line number Diff line number Diff line
@@ -31,14 +31,6 @@ void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int, 


/* MSRS */



#define MSR_LX_GLD_CONFIG    0x48002001

#define MSR_LX_GLCP_DOTPLL   0x4c000015

#define MSR_LX_DF_PADSEL     0x48002011

#define MSR_LX_DC_SPARE      0x80000011

#define MSR_LX_DF_GLCONFIG   0x48002001



#define MSR_LX_GLIU0_P2D_RO0 0x10000029



#define GLCP_DOTPLL_RESET    (1 << 0)

#define GLCP_DOTPLL_BYPASS   (1 << 15)

#define GLCP_DOTPLL_HALFPIX  (1 << 24)

drivers/video/geode/lxfb_ops.c

+10 −9
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/fb.h>

#include <linux/uaccess.h>

#include <linux/delay.h>

#include <asm/geode.h>



#include "lxfb.h"
@@ -101,7 +102,7 @@ static void lx_set_dotpll(u32 pllval) 
	u32 dotpll_lo, dotpll_hi;

	int i;



	rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);

	rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);



	if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))

		return;
@@ -110,7 +111,7 @@ static void lx_set_dotpll(u32 pllval) 
	dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);

	dotpll_lo |= GLCP_DOTPLL_RESET;



	wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);

	wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);



	/* Wait 100us for the PLL to lock */
@@ -119,7 +120,7 @@ static void lx_set_dotpll(u32 pllval) 
	/* Now, loop for the lock bit */



	for (i = 0; i < 1000; i++) {

		rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);

		rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);

		if (dotpll_lo & GLCP_DOTPLL_LOCK)

			break;

	}
@@ -127,7 +128,7 @@ static void lx_set_dotpll(u32 pllval) 
	/* Clear the reset bit */



	dotpll_lo &= ~GLCP_DOTPLL_RESET;

	wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);

	wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);

}



/* Set the clock based on the frequency specified by the current mode */
@@ -255,7 +256,7 @@ static void lx_graphics_enable(struct fb_info *info) 
		msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;

		msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;



		wrmsr(MSR_LX_DF_PADSEL, msrlo, msrhi);

		wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);

	}



	if (par->output & OUTPUT_CRT) {
@@ -321,7 +322,7 @@ void lx_set_mode(struct fb_info *info) 


	/* Set output mode */



	rdmsrl(MSR_LX_DF_GLCONFIG, msrval);

	rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);

	msrval &= ~DF_CONFIG_OUTPUT_MASK;



	if (par->output & OUTPUT_PANEL) {
@@ -335,7 +336,7 @@ void lx_set_mode(struct fb_info *info) 
		msrval |= DF_OUTPUT_CRT;

	}



	wrmsrl(MSR_LX_DF_GLCONFIG, msrval);

	wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);



	/* Clear the various buffers */

	/* FIXME:  Adjust for panning here */
@@ -383,13 +384,13 @@ void lx_set_mode(struct fb_info *info) 


	/* Set default watermark values */



	rdmsrl(MSR_LX_DC_SPARE, msrval);

	rdmsrl(MSR_LX_SPARE_MSR, msrval);



	msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |

		    DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |

		    DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);

	msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;

	wrmsrl(MSR_LX_DC_SPARE, msrval);

	wrmsrl(MSR_LX_SPARE_MSR, msrval);



	gcfg = DC_GCFG_DFLE;   /* Display fifo enable */

	gcfg |= 0xB600;         /* Set default priority */