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Commit 3294908b authored by Anson Huang's avatar Anson Huang Committed by Sasha Levin
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ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx 



[ Upstream commit 8aade778f787305fdbfd3c1d54e6b583601b5902 ]

i.MX6SX has bypass PMIC ready function, as this function
is normally NOT enabled on the board design, so we need
to bypass the PMIC ready pin check during DSM mode resume
flow, otherwise, the internal DSM resume logic will be
waiting for this signal to be ready forever and cause
resume fail.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Fixes: ff843d62 ("ARM: imx: add suspend support for i.mx6sx")
Cc: <stable@vger.kernel.org>
Tested-by: default avatarPeter Chen <peter.chen@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
parent 6000f01b

arch/arm/mach-imx/pm-imx6.c

+1 −1
Original line number Diff line number Diff line
@@ -293,7 +293,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) 
		val |= 0x3 << BP_CLPCR_STBY_COUNT;

		val |= BM_CLPCR_VSTBY;

		val |= BM_CLPCR_SBYOS;

		if (cpu_is_imx6sl())

		if (cpu_is_imx6sl() || cpu_is_imx6sx())

			val |= BM_CLPCR_BYPASS_PMIC_READY;

		if (cpu_is_imx6sl() || cpu_is_imx6sx())

			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;