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Commit 323d23ae authored by Kumar Gala's avatar Kumar Gala
Browse files

Revert "powerpc: Add support for early tlbilx opcode" 



This reverts commit e9965577.  Our HW
guys were able to fix this so it never sees the light of day.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 6329db8b

arch/powerpc/include/asm/mmu.h

+0 −6
Original line number Diff line number Diff line
@@ -52,12 +52,6 @@ 
 */

#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)



/* This indicates that the processor uses the wrong opcode for tlbilx

 * instructions.  During the ISA 2.06 development the opcode for tlbilx

 * changed and some early implementations used to old opcode

 */

#define MMU_FTR_TLBILX_EARLY_OPCODE	ASM_CONST(0x00400000)



#ifndef __ASSEMBLY__

#include <asm/cputable.h>

arch/powerpc/include/asm/ppc-opcode.h

+1 −10
Original line number Diff line number Diff line
@@ -44,7 +44,6 @@ 
#define PPC_INST_STSWI			0x7c0005aa

#define PPC_INST_STSWX			0x7c00052a

#define PPC_INST_TLBILX			0x7c000024

#define PPC_INST_TLBILX_EARLY		0x7c000626

#define PPC_INST_WAIT			0x7c00007c



/* macros to insert fields into opcodes */
@@ -64,18 +63,10 @@ 
#define PPC_RFDI		stringify_in_c(.long PPC_INST_RFDI)

#define PPC_RFMCI		stringify_in_c(.long PPC_INST_RFMCI)

#define PPC_TLBILX(t, a, b)	stringify_in_c(.long PPC_INST_TLBILX | \

					__PPC_T_TLB(t) | \

					__PPC_RA(a) | __PPC_RB(b))

					__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))

#define PPC_TLBILX_ALL(a, b)	PPC_TLBILX(0, a, b)

#define PPC_TLBILX_PID(a, b)	PPC_TLBILX(1, a, b)

#define PPC_TLBILX_VA(a, b)	PPC_TLBILX(3, a, b)



#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \

						__PPC_T_TLB(t) | \

						__PPC_RA(a) | __PPC_RB(b))

#define PPC_TLBILX_ALL_EARLY(a, b)	PPC_TLBILX_EARLY(0, a, b)

#define PPC_TLBILX_PID_EARLY(a, b)	PPC_TLBILX_EARLY(1, a, b)

#define PPC_TLBILX_VA_EARLY(a, b)	PPC_TLBILX_EARLY(3, a, b)

#define PPC_WAIT(w)		stringify_in_c(.long PPC_INST_WAIT | \

					__PPC_WC(w))

arch/powerpc/kernel/cputable.c

+1 −1
Original line number Diff line number Diff line
@@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_features		= CPU_FTRS_E500MC,

		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,

		.mmu_features		= MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |

			MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE,

			MMU_FTR_USE_TLBILX,

		.icache_bsize		= 64,

		.dcache_bsize		= 64,

		.num_pmcs		= 4,

arch/powerpc/mm/tlb_nohash_low.S

+1 −13
Original line number Diff line number Diff line
@@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION 
	andi.	r3,r3,MMUCSR0_TLBFI@l

	bne	1b

MMU_FTR_SECTION_ELSE

  BEGIN_MMU_FTR_SECTION_NESTED(96)

	PPC_TLBILX_ALL(0,r3)

  MMU_FTR_SECTION_ELSE_NESTED(96)

	PPC_TLBILX_ALL_EARLY(0,r3)

  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)

	PPC_TLBILX_ALL(0,0)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)

	msync

	isync
@@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION 
	wrteei	0

	mfspr	r4,SPRN_MAS6	/* save MAS6 */

	mtspr	SPRN_MAS6,r3

  BEGIN_MMU_FTR_SECTION_NESTED(96)

	PPC_TLBILX_PID(0,0)

  MMU_FTR_SECTION_ELSE_NESTED(96)

	PPC_TLBILX_PID_EARLY(0,0)

  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)

	mtspr	SPRN_MAS6,r4	/* restore MAS6 */

	wrtee	r10

MMU_FTR_SECTION_ELSE
@@ -193,11 +185,7 @@ BEGIN_MMU_FTR_SECTION 
	mtspr	SPRN_MAS1,r4

	tlbwe

MMU_FTR_SECTION_ELSE

  BEGIN_MMU_FTR_SECTION_NESTED(96)

	PPC_TLBILX_VA(0,r3)

  MMU_FTR_SECTION_ELSE_NESTED(96)

	PPC_TLBILX_VA_EARLY(0,r3)

  ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)

	msync

	isync