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Commit 30f83b37 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-nouveau-next' of... 

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

- GF117 acceleration support
- GK110 acceleration-with-blob-ucode support, and initial work towards
fixing our own ucode to be suitable.
- Large cleanups of fermi/kepler context handling

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (22 commits)
  drm/nva3/disp: Fix HDMI audio regression
  drm/nv50-/disp: Use output specific mask in interrupt
  drm/nouveau: use vmalloc for pgt allocation
  drm/nvc0-/gr: remove some more of the hardcoded register writes
  drm/nvc0-/gr: factor out yet more unknown magic into versioned functions
  drm/nvd7/devinit: use fermi class, not tesla
  drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16
  drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode
  drm/nvf0/gr: build cs ucode for GK110
  drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs
  drm/nvf0/gr: fix ddx shaders locking up on me
  drm/nvc0/devinit: minor typo
  drm/nvf0/gr: enable support, if external cs ucode is available
  drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding
  drm/nvf0/ce: enable support
  drm/nvf0/fifo: enable support
  drm/nvd7/gr: initial support
  drm/nvc0-/gr: generate cs register lists from grctx data
  drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs
  drm/nve0-/gr: some new gpc registers can have multiple copies
  ...
parents 6d35dea1 bf03d1b2

drivers/gpu/drm/nouveau/Makefile

+14 −2
Original line number Diff line number Diff line
@@ -200,7 +200,13 @@ nouveau-y += core/engine/fifo/nve0.o 
nouveau-y += core/engine/graph/ctxnv40.o

nouveau-y += core/engine/graph/ctxnv50.o

nouveau-y += core/engine/graph/ctxnvc0.o

nouveau-y += core/engine/graph/ctxnve0.o

nouveau-y += core/engine/graph/ctxnvc1.o

nouveau-y += core/engine/graph/ctxnvc3.o

nouveau-y += core/engine/graph/ctxnvc8.o

nouveau-y += core/engine/graph/ctxnvd7.o

nouveau-y += core/engine/graph/ctxnvd9.o

nouveau-y += core/engine/graph/ctxnve4.o

nouveau-y += core/engine/graph/ctxnvf0.o

nouveau-y += core/engine/graph/nv04.o

nouveau-y += core/engine/graph/nv10.o

nouveau-y += core/engine/graph/nv20.o
@@ -212,7 +218,13 @@ nouveau-y += core/engine/graph/nv35.o 
nouveau-y += core/engine/graph/nv40.o

nouveau-y += core/engine/graph/nv50.o

nouveau-y += core/engine/graph/nvc0.o

nouveau-y += core/engine/graph/nve0.o

nouveau-y += core/engine/graph/nvc1.o

nouveau-y += core/engine/graph/nvc3.o

nouveau-y += core/engine/graph/nvc8.o

nouveau-y += core/engine/graph/nvd7.o

nouveau-y += core/engine/graph/nvd9.o

nouveau-y += core/engine/graph/nve4.o

nouveau-y += core/engine/graph/nvf0.o

nouveau-y += core/engine/mpeg/nv31.o

nouveau-y += core/engine/mpeg/nv40.o

nouveau-y += core/engine/mpeg/nv50.o

drivers/gpu/drm/nouveau/core/engine/device/nvc0.c

+10 −10
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -104,7 +104,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -133,7 +133,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -161,7 +161,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -190,7 +190,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -291,7 +291,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;

		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;

		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;

		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_graph_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;

		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;

drivers/gpu/drm/nouveau/core/engine/device/nve0.c

+5 −7
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;

		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
@@ -105,7 +105,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;

		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
@@ -135,7 +135,7 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;

		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
@@ -163,16 +163,14 @@ nve0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;

#if 0

		device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;

#endif

		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;

		device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;

#if 0

		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;

		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;

		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;

#if 0

		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;

		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;

		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;

drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c

+4 −0
Original line number Diff line number Diff line
@@ -55,6 +55,10 @@ nva3_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data) 
	nv_wr32(priv, 0x61c510 + soff, 0x00000000);

	nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001);



	nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */

	nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */

	nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */



	/* ??? */

	nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */

	nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+5 −1
Original line number Diff line number Diff line
@@ -1107,6 +1107,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) 
	u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;

	u32 hval, hreg = 0x614200 + (head * 0x800);

	u32 oval, oreg;

	u32 mask;

	u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);

	if (conf != ~0) {

		if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
@@ -1133,6 +1134,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) 
			oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;

			oval = 0x00000000;

			hval = 0x00000000;

			mask = 0xffffffff;

		} else

		if (!outp.location) {

			if (outp.type == DCB_OUTPUT_DP)
@@ -1140,14 +1142,16 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) 
			oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;

			oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;

			hval = 0x00000000;

			mask = 0x00000707;

		} else {

			oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;

			oval = 0x00000001;

			hval = 0x00000001;

			mask = 0x00000707;

		}



		nv_mask(priv, hreg, 0x0000000f, hval);

		nv_mask(priv, oreg, 0x00000707, oval);

		nv_mask(priv, oreg, mask, oval);

	}

}