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Commit 30aacebe authored by Eugene Surovegin's avatar Eugene Surovegin Committed by Paul Mackerras
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[PATCH] ppc32: add 440GX erratum 440_43 workaround 



This patch adds workaround for PPC 440GX erratum 440_43. According to
this erratum spurious MachineChecks (caused by L1 cache parity) can
happen during DataTLB miss processing. We disable L1 cache parity
checking for 440GX rev.C and rev.F

Signed-off-by: default avatarEugene Surovegin <ebs@ebshome.net>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 1269277a

arch/ppc/platforms/4xx/ocotea.c

+1 −1
Original line number Diff line number Diff line
@@ -331,7 +331,7 @@ static void __init ocotea_init(void) 
void __init platform_init(unsigned long r3, unsigned long r4,

		unsigned long r5, unsigned long r6, unsigned long r7)

{

	ibm44x_platform_init(r3, r4, r5, r6, r7);

	ibm440gx_platform_init(r3, r4, r5, r6, r7);



	ppc_md.setup_arch = ocotea_setup_arch;

	ppc_md.show_cpuinfo = ocotea_show_cpuinfo;

arch/ppc/syslib/ibm440gx_common.c

+12 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * PPC440GX system library

 *

 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>

 * Copyright (c) 2003, 2004 Zultys Technologies

 * Copyright (c) 2003 - 2006 Zultys Technologies

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the
@@ -282,3 +282,14 @@ int ibm440gx_show_cpuinfo(struct seq_file *m){ 
	return 0;

}



void __init ibm440gx_platform_init(unsigned long r3, unsigned long r4,

				   unsigned long r5, unsigned long r6,

				   unsigned long r7)

{

	/* Erratum 440_43 workaround, disable L1 cache parity checking */

	if (!strcmp(cur_cpu_spec->cpu_name, "440GX Rev. C") ||

	    !strcmp(cur_cpu_spec->cpu_name, "440GX Rev. F"))

		mtspr(SPRN_CCR1, mfspr(SPRN_CCR1) | CCR1_DPC);



	ibm44x_platform_init(r3, r4, r5, r6, r7);

}

arch/ppc/syslib/ibm440gx_common.h

+4 −0
Original line number Diff line number Diff line
@@ -29,6 +29,10 @@ 
void ibm440gx_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk,

	unsigned int ser_clk) __init;



/* common 440GX platform init */

void ibm440gx_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,

			    unsigned long r6, unsigned long r7) __init;



/* Enable L2 cache */

void ibm440gx_l2c_enable(void) __init;

include/asm-ppc/reg_booke.h

+1 −0
Original line number Diff line number Diff line
@@ -237,6 +237,7 @@ do { \ 
#endif



/* Bit definitions for CCR1. */

#define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */

#define	CCR1_TCS	0x00000080 /* Timer Clock Select */



/* Bit definitions for the MCSR. */