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Commit 30963c0a authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
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x86, intel: Use c->microcode for Atom errata check 



Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Acked-by: default avatarH. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-2-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 506ed6b5

arch/x86/kernel/cpu/intel.c

+4 −11
Original line number Original line Diff line number Diff line
@@ -64,18 +64,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
	 * need the microcode to have already been loaded... so if it is

	 * need the microcode to have already been loaded... so if it is

	 * not, recommend a BIOS update and disable large pages.

	 * not, recommend a BIOS update and disable large pages.

	 */

	 */

	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {

	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&

		u32 ucode, junk;

	    c->microcode < 0x20e) {



		wrmsr(MSR_IA32_UCODE_REV, 0, 0);

		sync_core();

		rdmsr(MSR_IA32_UCODE_REV, junk, ucode);



		if (ucode < 0x20e) {

		printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");

		printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");

		clear_cpu_cap(c, X86_FEATURE_PSE);

		clear_cpu_cap(c, X86_FEATURE_PSE);

	}

	}

	}





#ifdef CONFIG_X86_64

#ifdef CONFIG_X86_64

	set_cpu_cap(c, X86_FEATURE_SYSENTER32);

	set_cpu_cap(c, X86_FEATURE_SYSENTER32);