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Commit 2ec6f254 authored by Alex Van Brunt's avatar Alex Van Brunt Committed by Ruchi Kandoi
Browse files

arm64: optionally set CP15BEN in SCTLR 



Setting CP15BEN allows legacy applications running in AArch32 mode
that use CP15 DMB as similar instructions to continue running.

Change-Id: If76d3c6ee12865ff8c4b4e7aed01146bead87773
Signed-off-by: default avatarAlex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/366096


Reviewed-by: default avatarRichard Wiley <rwiley@nvidia.com>
Tested-by: default avatarOskari Jaaskelainen <oskarij@nvidia.com>
parent 569ffcc0

arch/arm64/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -375,6 +375,17 @@ config ARCH_WANT_HUGE_PMD_SHARE 
config HAVE_ARCH_TRANSPARENT_HUGEPAGE

	def_bool y



config ARMV7_COMPAT_CP15_BARRIER

	bool "Allow applications to use the CP15 barrier operations"

	depends on ARMV7_COMPAT

	default y

	help

	 This option allows applications to use deprecated CP15 barrier

	 instructions. This is useful because this was the only way to create

	 a barrier on older ARM processors.



	 If you want to execute ARMv7 applications, say Y



config ARCH_HAS_CACHE_LINE_SIZE

	def_bool y

arch/arm64/mm/proc.S

+15 −0
Original line number Diff line number Diff line
@@ -243,6 +243,20 @@ ENTRY(__cpu_setup) 
	ret					// return to head.S

ENDPROC(__cpu_setup)



#ifdef CONFIG_ARMV7_COMPAT_CP15_BARRIER

	/*

	 *                 n n            T

	 *       U E      WT T UD     US IHBS

	 *       CE0      XWHW CZ     ME TEEA S

	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM

	 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved

	 * .... .100 .... 01.1 11.1 ..01 0011 1101 < software settings

	 */

	.type	crval, #object

crval:

	.word	0x030802e2			// clear

	.word	0x0405d13d			// set

#else

	/*

	 *                 n n            T

	 *       U E      WT T UD     US IHBS
@@ -255,3 +269,4 @@ ENDPROC(__cpu_setup) 
crval:

	.word	0x000802e2			// clear

	.word	0x0405d11d			// set

#endif