Merge "msm: kgsl: Correct the size of memlist entries in snapshot" (2e7e2407) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/gpu/msm/adreno.c

+9 −8

Original line number	Diff line number	Diff line
		@@ -1238,16 +1238,17 @@ static int adreno_init(struct kgsl_device *device)
		&adreno_dev->priv);
		}

		if (ADRENO_FEATURE(adreno_dev, ADRENO_PREEMPTION))
		set_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv);
		if (ADRENO_FEATURE(adreno_dev, ADRENO_PREEMPTION)) {
		int r = 0;

		/* disable preemption for no mmu mode */
		if (kgsl_mmu_get_mmutype() == KGSL_MMU_TYPE_NONE)
		adreno_preemption_disable(adreno_dev);
		if (gpudev->preemption_init)
		r = gpudev->preemption_init(adreno_dev);

		/* Initialize preemption here */
		if (gpudev->preemption_init && adreno_is_preemption_enabled(adreno_dev))
		gpudev->preemption_init(adreno_dev);
		if (r == 0)
		set_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv);
		else
		WARN(1, "adreno: GPU preemption is disabled\n");
		}

		if (gpudev->cp_crash_dumper_init)
		gpudev->cp_crash_dumper_init(adreno_dev);

drivers/gpu/msm/adreno.h

+1 −6

Original line number	Diff line number	Diff line
		@@ -679,7 +679,7 @@ struct adreno_gpudev {
		int (preemption_token)(struct adreno_device ,
		struct adreno_ringbuffer , unsigned int ,
		uint64_t gpuaddr);
		void (preemption_init)(struct adreno_device );
		int (preemption_init)(struct adreno_device );
		void (preemption_schedule)(struct adreno_device );
		void (enable_64bit)(struct adreno_device );
		void (cp_crash_dumper_init)(struct adreno_device );
		@@ -1340,11 +1340,6 @@ void adreno_writereg64(struct adreno_device *adreno_dev,
		unsigned int adreno_iommu_set_apriv(struct adreno_device *adreno_dev,
		unsigned int *cmds, int set);

		static inline void adreno_preemption_disable(struct adreno_device *adreno_dev)
		{
		clear_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv);
		}

		static inline bool adreno_is_preemption_enabled(
		struct adreno_device *adreno_dev)
		{

drivers/gpu/msm/adreno_a5xx.c

+40 −53

Original line number	Diff line number	Diff line
		@@ -162,35 +162,39 @@ static void a5xx_preemption_save(struct adreno_device *adreno_dev,
		PREEMPT_RECORD(rptr));
		}

		/*
		* a5xx_preemption_init() - Init preemption
		*/
		static void a5xx_preemption_init(struct adreno_device *adreno_dev)
		static int a5xx_preemption_init(struct adreno_device *adreno_dev)
		{
		struct kgsl_device *device = &adreno_dev->dev;
		struct kgsl_iommu *iommu = device->mmu.priv;
		struct adreno_ringbuffer *rb;
		uint i, ret;
		uint64_t gaddr;
		int ret;
		unsigned int i;
		uint64_t addr;

		if (!adreno_is_preemption_enabled(adreno_dev))
		return;
		/* We are dependent on IOMMU to make preemption go on the CP side */
		if (kgsl_mmu_get_mmutype() != KGSL_MMU_TYPE_IOMMU)
		return -ENODEV;

		/* Allocate mem for storing preemption counters */
		ret = kgsl_allocate_global(device, &adreno_dev->preemption_counters,
		PAGE_SIZE, 0, 0);
		adreno_dev->num_ringbuffers *
		A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE, 0, 0);
		if (ret)
		return ret;

		addr = adreno_dev->preemption_counters.gpuaddr;

		/* Allocate mem for storing preemption switch record */
		FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
		ret = kgsl_allocate_global(&adreno_dev->dev,
		&rb->preemption_desc,
		A5XX_CP_CTXRECORD_SIZE_IN_BYTES, 0,
		KGSL_MEMDESC_PRIVILEGED);
		if (!ret) {
		&rb->preemption_desc, A5XX_CP_CTXRECORD_SIZE_IN_BYTES,
		0, KGSL_MEMDESC_PRIVILEGED);
		if (ret)
		return ret;

		/* Initialize the context switch record here */
		kgsl_sharedmem_writel(rb->device, &rb->preemption_desc,
		PREEMPT_RECORD(magic),
		A5XX_CP_CTXRECORD_MAGIC_REF);
		PREEMPT_RECORD(magic), A5XX_CP_CTXRECORD_MAGIC_REF);
		kgsl_sharedmem_writel(rb->device, &rb->preemption_desc,
		PREEMPT_RECORD(info), 0);
		kgsl_sharedmem_writel(rb->device, &rb->preemption_desc,
		@@ -204,32 +208,15 @@ static void a5xx_preemption_init(struct adreno_device *adreno_dev)
		kgsl_sharedmem_writeq(rb->device, &rb->preemption_desc,
		PREEMPT_RECORD(rbase),
		adreno_dev->ringbuffers[i].buffer_desc.gpuaddr);
		gaddr = (adreno_dev->preemption_counters.gpuaddr +
		i*A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE_IN_DWORDS);

		if ((gaddr - adreno_dev->preemption_counters.gpuaddr)
		< PAGE_SIZE) {
		kgsl_sharedmem_writeq(rb->device,
		&rb->preemption_desc,
		offsetof(
		struct a5xx_cp_preemption_record,
		counter), gaddr);
		} else
		KGSL_DRV_ERR(device,
		"Insufficient memory for preemption counters\n");
		} else {
		adreno_preemption_disable(adreno_dev);
		WARN(1, "gpu preemption: disabled due to low memory");
		}
		kgsl_sharedmem_writeq(rb->device, &rb->preemption_desc,
		PREEMPT_RECORD(counter), addr);

		addr += A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE;
		}

		/* Allocate mem for storing preemption smmu record */
		ret = kgsl_allocate_global(device, &iommu->smmu_info, PAGE_SIZE,
		return kgsl_allocate_global(device, &iommu->smmu_info, PAGE_SIZE,
		KGSL_MEMDESC_PRIVILEGED, 0);
		if (ret) {
		adreno_preemption_disable(adreno_dev);
		WARN(1, "preemption: disabled due to low memory");
		}
		}

		/*

drivers/gpu/msm/adreno_a5xx.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -17,8 +17,8 @@
		#define A5XX_CP_CTXRECORD_MAGIC_REF 0x27C4BAFCUL
		/* Size of each CP preemption record */
		#define A5XX_CP_CTXRECORD_SIZE_IN_BYTES 0x100000
		/* Size of ctx_rec_PRCNT below */
		#define A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE_IN_DWORDS 16
		/* Size of the preemption counter block (in bytes) */
		#define A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE (16 * 4)

		/**
		* struct a5xx_cp_preemption_record - CP context record for

drivers/gpu/msm/adreno_ioctl.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -87,8 +87,7 @@ static long adreno_ioctl_preemption_counters_query(
		struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_priv->device);
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		struct kgsl_preemption_counters_query *read = data;
		int size_level = A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE_IN_DWORDS *
		sizeof(unsigned int);
		int size_level = A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE;
		int levels_to_copy;

		if (!adreno_is_a5xx(adreno_dev) \|\|