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Commit 2e72b406 authored by Andrei Danaila's avatar Andrei Danaila Committed by Matt Wagantall
Browse files

msm: mhi: Flush pending writes on D3hot and M2 



Flush pending PCIe writes after setting D3 hot and after
setting M2. This will ensure that no writes will bring the link
down as it is being turned off.

CRs-Fixed: 755658
Change-Id: If2ca4575f833ede77d6a14e1e2bf5a86d1c28218
Signed-off-by: default avatarAndrei Danaila <adanaila@codeaurora.org>
parent 2276b6f4

drivers/platform/msm/mhi/mhi_main.c

+0 −4
Original line number Diff line number Diff line
@@ -1458,10 +1458,6 @@ void mhi_reg_write(struct mhi_device_ctxt *mhi_dev_ctxt, 
					io_addr, io_offset, val);

	iowrite32(val, io_addr + io_offset);

	wmb();

	msm_pcie_pm_control(MSM_PCIE_REQ_EXIT_L1,

			mhi_dev_ctxt->dev_info->pcie_device->bus->number,

			mhi_dev_ctxt->dev_info->pcie_device,

			NULL, 0);

}



u32 mhi_reg_read_field(void __iomem *io_addr, uintptr_t io_offset,

drivers/platform/msm/mhi/mhi_pm.c

+10 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -226,6 +226,15 @@ enum MHI_STATUS mhi_turn_off_pcie_link(struct mhi_device_ctxt *mhi_dev_ctxt) 
		ret_val = MHI_STATUS_ERROR;

		goto exit;

	}

	r = msm_pcie_pm_control(MSM_PCIE_REQ_EXIT_L1,

			mhi_dev_ctxt->dev_info->pcie_device->bus->number,

			mhi_dev_ctxt->dev_info->pcie_device,

			NULL, 0);

	if (r) {

		mhi_log(MHI_MSG_CRITICAL,

			"Failed failed to exit L1: %x\n", r);

	}



	r = msm_pcie_pm_control(MSM_PCIE_SUSPEND,

			mhi_dev_ctxt->dev_info->pcie_device->bus->number,

			mhi_dev_ctxt->dev_info->pcie_device,

drivers/platform/msm/mhi/mhi_states.c

+1 −0
Original line number Diff line number Diff line
@@ -202,6 +202,7 @@ static enum MHI_STATUS process_m1_transition( 
			MHICTRL_MHISTATE_MASK,

			MHICTRL_MHISTATE_SHIFT,

			MHI_STATE_M2);

		mhi_reg_read(mhi_dev_ctxt->mmio_addr, MHICTRL);

		mhi_dev_ctxt->counters.m1_m2++;

	}

	write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);