Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2e1e6dad authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: remove special handling for the DMA ring 



Now that we have callbacks for [rw]ptr handling we can
remove the special handling for the DMA rings and use
the callbacks instead.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 02c9f7fa

drivers/gpu/drm/radeon/cik.c

+8 −12
Original line number Diff line number Diff line
@@ -3414,7 +3414,6 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, 
		cik_srbm_select(rdev, 0, 0, 0, 0);

		mutex_unlock(&rdev->srbm_mutex);

	}

	rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;



	return rptr;

}
@@ -3433,7 +3432,6 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 
		cik_srbm_select(rdev, 0, 0, 0, 0);

		mutex_unlock(&rdev->srbm_mutex);

	}

	wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;



	return wptr;

}
@@ -3441,10 +3439,8 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, 
void cik_compute_ring_set_wptr(struct radeon_device *rdev,

			       struct radeon_ring *ring)

{

	u32 wptr = (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask;



	rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(wptr);

	WDOORBELL32(ring->doorbell_offset, wptr);

	rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr);

	WDOORBELL32(ring->doorbell_offset, ring->wptr);

}



/**
@@ -7649,7 +7645,7 @@ static int cik_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     CP_RB0_RPTR, CP_RB0_WPTR,

			     0, 0xfffff, RADEON_CP_PACKET2);

			     RADEON_CP_PACKET2);

	if (r)

		return r;
@@ -7658,7 +7654,7 @@ static int cik_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,

			     CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,

			     0, 0xfffff, PACKET3(PACKET3_NOP, 0x3FFF));

			     PACKET3(PACKET3_NOP, 0x3FFF));

	if (r)

		return r;

	ring->me = 1; /* first MEC */
@@ -7670,7 +7666,7 @@ static int cik_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,

			     CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR,

			     0, 0xffffffff, PACKET3(PACKET3_NOP, 0x3FFF));

			     PACKET3(PACKET3_NOP, 0x3FFF));

	if (r)

		return r;

	/* dGPU only have 1 MEC */
@@ -7683,7 +7679,7 @@ static int cik_startup(struct radeon_device *rdev) 
	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,

			     SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,

			     2, 0xfffffffc, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

			     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

	if (r)

		return r;
@@ -7691,7 +7687,7 @@ static int cik_startup(struct radeon_device *rdev) 
	r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,

			     SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,

			     SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET,

			     2, 0xfffffffc, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

			     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

	if (r)

		return r;
@@ -7707,7 +7703,7 @@ static int cik_startup(struct radeon_device *rdev) 
	if (ring->ring_size) {

		r = radeon_ring_init(rdev, ring, ring->ring_size, 0,

				     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,

				     0, 0xfffff, RADEON_CP_PACKET2);

				     RADEON_CP_PACKET2);

		if (!r)

			r = r600_uvd_init(rdev, true);

		if (r)

drivers/gpu/drm/radeon/evergreen.c

+3 −3
Original line number Diff line number Diff line
@@ -5268,14 +5268,14 @@ static int evergreen_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,

			     0, 0xfffff, RADEON_CP_PACKET2);

			     RADEON_CP_PACKET2);

	if (r)

		return r;



	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     DMA_RB_RPTR, DMA_RB_WPTR,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));

			     DMA_PACKET(DMA_PACKET_NOP, 0, 0));

	if (r)

		return r;
@@ -5293,7 +5293,7 @@ static int evergreen_startup(struct radeon_device *rdev) 
	if (ring->ring_size) {

		r = radeon_ring_init(rdev, ring, ring->ring_size, 0,

				     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,

				     0, 0xfffff, RADEON_CP_PACKET2);

				     RADEON_CP_PACKET2);

		if (!r)

			r = r600_uvd_init(rdev, true);

drivers/gpu/drm/radeon/ni.c

+4 −4
Original line number Diff line number Diff line
@@ -2192,7 +2192,7 @@ static int cayman_startup(struct radeon_device *rdev) 


	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     CP_RB0_RPTR, CP_RB0_WPTR,

			     0, 0xfffff, RADEON_CP_PACKET2);

			     RADEON_CP_PACKET2);

	if (r)

		return r;
@@ -2200,7 +2200,7 @@ static int cayman_startup(struct radeon_device *rdev) 
	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     DMA_RB_RPTR + DMA0_REGISTER_OFFSET,

			     DMA_RB_WPTR + DMA0_REGISTER_OFFSET,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

			     DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	if (r)

		return r;
@@ -2208,7 +2208,7 @@ static int cayman_startup(struct radeon_device *rdev) 
	r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,

			     DMA_RB_RPTR + DMA1_REGISTER_OFFSET,

			     DMA_RB_WPTR + DMA1_REGISTER_OFFSET,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

			     DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	if (r)

		return r;
@@ -2227,7 +2227,7 @@ static int cayman_startup(struct radeon_device *rdev) 
	if (ring->ring_size) {

		r = radeon_ring_init(rdev, ring, ring->ring_size, 0,

				     UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,

				     0, 0xfffff, RADEON_CP_PACKET2);

				     RADEON_CP_PACKET2);

		if (!r)

			r = r600_uvd_init(rdev, true);

		if (r)

drivers/gpu/drm/radeon/r100.c

+1 −1
Original line number Diff line number Diff line
@@ -1102,7 +1102,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 
	r100_cp_load_microcode(rdev);

	r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,

			     0, 0x7fffff, RADEON_CP_PACKET2);

			     RADEON_CP_PACKET2);

	if (r) {

		return r;

	}

drivers/gpu/drm/radeon/r600.c

+45 −2
Original line number Diff line number Diff line
@@ -2504,6 +2504,49 @@ void r600_cp_fini(struct radeon_device *rdev) 
 * solid fills, and a number of other things.  It also

 * has support for tiling/detiling of buffers.

 */



/**

 * r600_dma_get_rptr - get the current read pointer

 *

 * @rdev: radeon_device pointer

 * @ring: radeon ring pointer

 *

 * Get the current rptr from the hardware (r6xx+).

 */

uint32_t r600_dma_get_rptr(struct radeon_device *rdev,

			   struct radeon_ring *ring)

{

	return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2;

}



/**

 * r600_dma_get_wptr - get the current write pointer

 *

 * @rdev: radeon_device pointer

 * @ring: radeon ring pointer

 *

 * Get the current wptr from the hardware (r6xx+).

 */

uint32_t r600_dma_get_wptr(struct radeon_device *rdev,

			   struct radeon_ring *ring)

{

	return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2;

}



/**

 * r600_dma_set_wptr - commit the write pointer

 *

 * @rdev: radeon_device pointer

 * @ring: radeon ring pointer

 *

 * Write the wptr back to the hardware (r6xx+).

 */

void r600_dma_set_wptr(struct radeon_device *rdev,

		       struct radeon_ring *ring)

{

	WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc);

}



/**

 * r600_dma_stop - stop the async dma engine

 *
@@ -3386,14 +3429,14 @@ static int r600_startup(struct radeon_device *rdev) 
	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,

			     0, 0xfffff, RADEON_CP_PACKET2);

			     RADEON_CP_PACKET2);

	if (r)

		return r;



	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,

			     DMA_RB_RPTR, DMA_RB_WPTR,

			     2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

			     DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

	if (r)

		return r;