Commit 2dbac102 authored Oct 13, 2008 by David Daney Committed by Ralf Baechle Oct 15, 2008

MIPS: Align .data.cacheline_aligned based on CONFIG_MIPS_L1_CACHE_SHIFT



Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent e47c659b

arch/mips/kernel/vmlinux.lds.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -104,7 +104,7 @@ SECTIONS
		. = ALIGN(_PAGE_SIZE);
		__nosave_end = .;

		. = ALIGN(32);
		. = ALIGN(1 << CONFIG_MIPS_L1_CACHE_SHIFT);
		.data.cacheline_aligned : {
		*(.data.cacheline_aligned)
		}