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Commit 2d9e667e authored by David Woodhouse's avatar David Woodhouse
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intel-iommu: Force-disable IOMMU for iGFX on broken Cantiga revisions. 



Certain revisions of this chipset appear to be broken. There is a shadow
GTT which mirrors the real GTT but contains pre-translated physical
addresses, for performance reasons. When a GTT update happens, the
translations are done once and the resulting physical addresses written
back to the shadow GTT.

Except sometimes, the physical address is actually written back to the
_real_ GTT, not the shadow GTT. Thus we start to see faults when that
physical address is fed through translation again.

Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent 00dfff77

drivers/pci/intel-iommu.c

+7 −1
Original line number Diff line number Diff line
@@ -340,7 +340,7 @@ int dmar_disabled = 0; 
int dmar_disabled = 1;

#endif /*CONFIG_DMAR_DEFAULT_ON*/



static int __initdata dmar_map_gfx = 1;

static int dmar_map_gfx = 1;

static int dmar_forcedac;

static int intel_iommu_strict;
@@ -3721,6 +3721,12 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) 
	 */

	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");

	rwbf_quirk = 1;



	/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */

	if (dev->revision == 0x07) {

		printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");

		dmar_map_gfx = 0;

	}

}



DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);