Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2d401b17 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Don't use pipe_offset stuff for DPLL registers 



These are just single registers so wasting space for the pipe offsets
seems a bit pointless. So just use the _PIPE3() macro instead.

Also rewrite the _PIPE3() macro to be more obvious, and protect the
arguments properly.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
[danvet: Frob conflict.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 61407f6d

drivers/gpu/drm/i915/i915_drv.c

+0 −6
Original line number Diff line number Diff line
@@ -46,8 +46,6 @@ static struct drm_driver driver; 
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \

	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \

	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \

	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }



#define GEN_CHV_PIPEOFFSETS \
@@ -55,10 +53,6 @@ static struct drm_driver driver; 
			  CHV_PIPE_C_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   CHV_TRANSCODER_C_OFFSET, }, \

	.dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \

			  CHV_DPLL_C_OFFSET }, \

	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \

			     CHV_DPLL_C_MD_OFFSET }, \

	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \

			     CHV_PALETTE_C_OFFSET }

drivers/gpu/drm/i915/i915_drv.h

+0 −2
Original line number Diff line number Diff line
@@ -552,8 +552,6 @@ struct intel_device_info { 
	/* Register offsets for the various display pipes and transcoders */

	int pipe_offsets[I915_MAX_TRANSCODERS];

	int trans_offsets[I915_MAX_TRANSCODERS];

	int dpll_offsets[I915_MAX_PIPES];

	int dpll_md_offsets[I915_MAX_PIPES];

	int palette_offsets[I915_MAX_PIPES];

	int cursor_offsets[I915_MAX_PIPES];

};

drivers/gpu/drm/i915/i915_reg.h

+10 −16
Original line number Diff line number Diff line
@@ -29,8 +29,8 @@ 
#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))



#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))

#define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c)

#define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c)

#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \

			       (pipe) == PIPE_B ? (b) : (c))



#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))

#define _MASKED_BIT_DISABLE(a) ((a) << 16)
@@ -1605,11 +1605,10 @@ enum punit_power_well { 
/*

 * Clock control & power management

 */

#define DPLL_A_OFFSET 0x6014

#define DPLL_B_OFFSET 0x6018

#define CHV_DPLL_C_OFFSET 0x6030

#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \

		    dev_priv->info.display_mmio_offset)

#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)

#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)

#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)

#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)



#define VGA0	0x6000

#define VGA1	0x6004
@@ -1697,11 +1696,10 @@ enum punit_power_well { 
#define   SDVO_MULTIPLIER_SHIFT_HIRES		4

#define   SDVO_MULTIPLIER_SHIFT_VGA		0



#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */

#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */

#define CHV_DPLL_C_MD_OFFSET 0x603c

#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \

		       dev_priv->info.display_mmio_offset)

#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)

#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)

#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)

#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)



/*

 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
@@ -6449,9 +6447,5 @@ enum punit_power_well { 
/* For UMS only (deprecated): */

#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)

#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)

#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)

#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)

#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)

#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)



#endif /* _I915_REG_H_ */