ARM: pxa168: added wake clear register support for APMU

#define APMU_FNRST_DIS	(1 << 1)

#define APMU_AXIRST_DIS	(1 << 0)

/* Wake Clear Register */

#define APMU_WAKE_CLR	APMU_REG(0x07c)

#define APMU_PXA168_KP_WAKE_CLR		(1 << 7)

#define APMU_PXA168_CFI_WAKE_CLR	(1 << 6)

#define APMU_PXA168_XD_WAKE_CLR		(1 << 5)

#define APMU_PXA168_MSP_WAKE_CLR	(1 << 4)

#define APMU_PXA168_SD4_WAKE_CLR	(1 << 3)

#define APMU_PXA168_SD3_WAKE_CLR	(1 << 2)

#define APMU_PXA168_SD2_WAKE_CLR	(1 << 1)

#define APMU_PXA168_SD1_WAKE_CLR	(1 << 0)

#endif /* __ASM_MACH_REGS_APMU_H */