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Commit 2b1be677 authored by Nadav Har'El's avatar Nadav Har'El Committed by Paolo Bonzini
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nEPT: Some additional comments 



Some additional comments to preexisting code:
Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
Don't mention "shadow on either EPT or shadow" as the only two options.

Reviewed-by: default avatarXiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Signed-off-by: default avatarNadav Har'El <nyh@il.ibm.com>
Signed-off-by: default avatarJun Nakajima <jun.nakajima@intel.com>
Signed-off-by: default avatarXinhao Xu <xinhao.xu@intel.com>
Signed-off-by: default avatarYang Zhang <yang.z.zhang@Intel.com>
Signed-off-by: default avatarGleb Natapov <gleb@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent afa61f75

arch/x86/kvm/vmx.c

+13 −0
Original line number Diff line number Diff line
@@ -6669,7 +6669,20 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) 
		return nested_cpu_has2(vmcs12,

			SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);

	case EXIT_REASON_EPT_VIOLATION:

		/*

		 * L0 always deals with the EPT violation. If nested EPT is

		 * used, and the nested mmu code discovers that the address is

		 * missing in the guest EPT table (EPT12), the EPT violation

		 * will be injected with nested_ept_inject_page_fault()

		 */

		return 0;

	case EXIT_REASON_EPT_MISCONFIG:

		/*

		 * L2 never uses directly L1's EPT, but rather L0's own EPT

		 * table (shadow on EPT) or a merged EPT table that L0 built

		 * (EPT on EPT). So any problems with the structure of the

		 * table is L0's fault.

		 */

		return 0;

	case EXIT_REASON_PREEMPTION_TIMER:

		return vmcs12->pin_based_vm_exec_control &