Merge "msm: kgsl: Enable GPU-BIMC clocks from kernel driver" (2a92be13) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/devicetree/bindings/gpu/adreno.txt

+3 −1

Original line number	Diff line number	Diff line
		@@ -16,7 +16,9 @@ Required properties:
		- interrupts: Interrupt mapping for GPU IRQ.
		- interrupt-names: String property to describe the name of the interrupt.
		- qcom,id: An integer used as an identification number for the device.

		- qcom,gpu-bimc-interface-clk-freq:
		GPU-BIMC interface clock needs to be set to this value for
		targets where B/W requirements does not meet GPU Turbo use cases.
		- clocks: List of phandle and clock specifier pairs, one pair
		for each clock input to the device.
		- clock-names: List of clock input name strings sorted in the same

arch/arm/boot/dts/qcom/msmgold-gpu.dtsi

+4 −2

Original line number	Diff line number	Diff line
		@@ -53,17 +53,19 @@

		qcom,idle-timeout = <80>; //msecs
		qcom,strtstp-sleepwake;
		qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,
		<&clock_gcc clk_gcc_oxili_ahb_clk>,
		<&clock_gcc clk_gcc_bimc_gfx_clk>,
		<&clock_gcc clk_gcc_bimc_gpu_clk>,
		<&clock_gcc clk_gcc_gtcu_ahb_clk>,
		<&clock_gcc clk_gcc_gfx_tcu_clk>;
		<&clock_gcc clk_gcc_gfx_tcu_clk>,
		<&clock_gcc clk_bimc_gpu_clk>;

		clock-names = "core_clk", "iface_clk", "mem_iface_clk",
		"alt_mem_iface_clk", "gtcu_iface_clk",
		"gtcu_clk";
		"gtcu_clk", "bimc_gpu_clk";

		/* Bus Scale Settings */
		qcom,gpubw-dev = <&gpubw>;

drivers/gpu/msm/kgsl_pwrctrl.c

+50 −0

Original line number	Diff line number	Diff line
		@@ -387,6 +387,28 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device,
		pwr->active_pwrlevel, pwrlevel->gpu_freq,
		pwr->previous_pwrlevel,
		pwr->pwrlevels[old_level].gpu_freq);

		/*
		* Some targets do not support the bandwidth requirement of
		* GPU at TURBO, for such targets we need to set GPU-BIMC
		* interface clocks to TURBO directly whenever GPU runs at
		* TURBO. The TURBO frequency of gfx-bimc need to be defined
		* in target device tree.
		*/
		if (pwr->gpu_bimc_int_clk) {
		if (pwr->active_pwrlevel == 0 &&
		!pwr->gpu_bimc_interface_enabled) {
		clk_set_rate(pwr->gpu_bimc_int_clk,
		pwr->gpu_bimc_int_clk_freq);
		clk_prepare_enable(pwr->gpu_bimc_int_clk);
		pwr->gpu_bimc_interface_enabled = 1;
		} else if (pwr->previous_pwrlevel == 0
		&& pwr->gpu_bimc_interface_enabled) {
		clk_disable_unprepare(pwr->gpu_bimc_int_clk);
		pwr->gpu_bimc_interface_enabled = 0;
		}
		}

		/* Change register settings if any AFTER pwrlevel change*/
		kgsl_pwrctrl_pwrlevel_change_settings(device, 1);

		@@ -1310,6 +1332,13 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
		&pwr->power_flags)) {
		trace_kgsl_clk(device, state,
		kgsl_pwrctrl_active_freq(pwr));
		/* Disable gpu-bimc-interface clocks */
		if (pwr->gpu_bimc_int_clk &&
		pwr->gpu_bimc_interface_enabled) {
		clk_disable_unprepare(pwr->gpu_bimc_int_clk);
		pwr->gpu_bimc_interface_enabled = 0;
		}

		for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
		clk_disable(pwr->grp_clks[i]);
		/* High latency clock maintenance. */
		@@ -1352,6 +1381,17 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
		this is to let GPU interrupt to come */
		for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
		clk_enable(pwr->grp_clks[i]);
		/* Enable the gpu-bimc-interface clocks */
		if (pwr->gpu_bimc_int_clk) {
		if (pwr->active_pwrlevel == 0 &&
		!pwr->gpu_bimc_interface_enabled) {
		clk_set_rate(pwr->gpu_bimc_int_clk,
		pwr->gpu_bimc_int_clk_freq);
		clk_prepare_enable(
		pwr->gpu_bimc_int_clk);
		pwr->gpu_bimc_interface_enabled = 1;
		}
		}
		}
		}
		}
		@@ -1662,6 +1702,13 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
		}
		}

		/* Getting gfx-bimc-interface-clk frequency */
		if (!of_property_read_u32(pdev->dev.of_node,
		"qcom,gpu-bimc-interface-clk-freq",
		&pwr->gpu_bimc_int_clk_freq))
		pwr->gpu_bimc_int_clk = devm_clk_get(&pdev->dev,
		"bimc_gpu_clk");

		pwr->power_flags = BIT(KGSL_PWRFLAGS_RETENTION_ON);

		if (pwr->num_pwrlevels == 0) {
		@@ -1843,6 +1890,9 @@ void kgsl_pwrctrl_close(struct kgsl_device *device)
		for (i = 0; i < KGSL_MAX_REGULATORS; i++)
		pwr->grp_clks[i] = NULL;

		if (pwr->gpu_bimc_int_clk)
		devm_clk_put(&device->pdev->dev, pwr->gpu_bimc_int_clk);

		pwr->power_flags = 0;

		if (!IS_ERR_OR_NULL(pwr->sysfs_pwr_limit)) {

drivers/gpu/msm/kgsl_pwrctrl.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -160,6 +160,7 @@ struct kgsl_pwrctrl {
		int interrupt_num;
		struct clk *grp_clks[KGSL_MAX_CLKS];
		struct clk *dummy_mx_clk;
		struct clk *gpu_bimc_int_clk;
		unsigned long power_flags;
		unsigned long ctrl_flags;
		struct kgsl_pwrlevel pwrlevels[KGSL_MAX_PWRLEVELS];
		@@ -204,6 +205,8 @@ struct kgsl_pwrctrl {
		struct timer_list deep_nap_timer;
		uint32_t deep_nap_timeout;
		bool gx_retention;
		unsigned int gpu_bimc_int_clk_freq;
		bool gpu_bimc_interface_enabled;
		};

		int kgsl_pwrctrl_init(struct kgsl_device *device);