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Commit 2a919596 authored by Jack Steiner's avatar Jack Steiner Committed by Ingo Molnar
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x86, UV: Add support for SGI UV2 hub chip 



This patch adds support for a new version of the SGI UV hub
chip. The hub chip is the node controller that connects multiple
blades into a larger coherent SSI.

For the most part, UV2 is compatible with UV1. The majority of
the changes are in the addresses of MMRs and in a few cases, the
contents of MMRs. These changes are the result in changes in the
system topology such as node configuration, processor types,
maximum nodes, physical address sizes, etc.

Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
Link: http://lkml.kernel.org/r/20110511175028.GA18006@sgi.com


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 7ccafc5f

arch/x86/include/asm/uv/uv_bau.h

+38 −4
Original line number Diff line number Diff line
@@ -44,7 +44,10 @@ 
#define UV_ACT_STATUS_SIZE		2

#define UV_DISTRIBUTION_SIZE		256

#define UV_SW_ACK_NPENDING		8

#define UV_NET_ENDPOINT_INTD		0x38

#define UV1_NET_ENDPOINT_INTD		0x38

#define UV2_NET_ENDPOINT_INTD		0x28

#define UV_NET_ENDPOINT_INTD		(is_uv1_hub() ?			\

			UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)

#define UV_DESC_BASE_PNODE_SHIFT	49

#define UV_PAYLOADQ_PNODE_SHIFT		49

#define UV_PTC_BASENAME			"sgi_uv/ptc_statistics"
@@ -53,10 +56,22 @@ 
#define UV_BAU_TUNABLES_FILE		"bau_tunables"

#define WHITESPACE			" \t\n"

#define uv_physnodeaddr(x)		((__pa((unsigned long)(x)) & uv_mmask))

#define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15

#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16

#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x0000000009UL





/* [19:16] SOFT_ACK timeout period  19: 1 is urgency 7  17:16 1 is multiplier */

/*

 * UV2: Bit 19 selects between

 *  (0): 10 microsecond timebase and

 *  (1): 80 microseconds

 *  we're using 655us, similar to UV1: 65 units of 10us

 */

#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)

#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL)



#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD	(is_uv1_hub() ?			\

		UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD :			\

		UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)



#define BAU_MISC_CONTROL_MULT_MASK 3



#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
@@ -76,6 +91,16 @@ 
#define DESC_STATUS_ACTIVE		1

#define DESC_STATUS_DESTINATION_TIMEOUT	2

#define DESC_STATUS_SOURCE_TIMEOUT	3

/*

 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2

 * values 1 and 5 will not occur

 */

#define UV2H_DESC_IDLE			0

#define UV2H_DESC_DEST_TIMEOUT		2

#define UV2H_DESC_DEST_STRONG_NACK	3

#define UV2H_DESC_BUSY			4

#define UV2H_DESC_SOURCE_TIMEOUT	6

#define UV2H_DESC_DEST_PUT_ERR		7



/*

 * delay for 'plugged' timeout retries, in microseconds
@@ -96,6 +121,15 @@ 


#define UV_LB_SUBNODEID 0x10



/* these two are the same for UV1 and UV2: */

#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT

#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK

/* 4 bits of software ack period */

#define UV2_ACK_MASK 0x7UL

#define UV2_ACK_UNITS_SHFT 3

#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT

#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT



/*

 * number of entries in the destination side payload queue

 */

arch/x86/include/asm/uv/uv_hub.h

+58 −13
Original line number Diff line number Diff line
@@ -77,8 +77,9 @@ 
 *

 *		1111110000000000

 *		5432109876543210

 *		pppppppppplc0cch	Nehalem-EX

 *		ppppppppplcc0cch	Westmere-EX

 *		pppppppppplc0cch	Nehalem-EX (12 bits in hdw reg)

 *		ppppppppplcc0cch	Westmere-EX (12 bits in hdw reg)

 *		pppppppppppcccch	SandyBridge (15 bits in hdw reg)

 *		sssssssssss

 *

 *			p  = pnode bits
@@ -87,7 +88,7 @@ 
 *			h  = hyperthread

 *			s  = bits that are in the SOCKET_ID CSR

 *

 *	Note: Processor only supports 12 bits in the APICID register. The ACPI

 *	Note: Processor may support fewer bits in the APICID register. The ACPI

 *	      tables hold all 16 bits. Software needs to be aware of this.

 *

 *	      Unless otherwise specified, all references to APICID refer to
@@ -138,6 +139,8 @@ struct uv_hub_info_s { 
	unsigned long		global_mmr_base;

	unsigned long		gpa_mask;

	unsigned int		gnode_extra;

	unsigned char		hub_revision;

	unsigned char		apic_pnode_shift;

	unsigned long		gnode_upper;

	unsigned long		lowmem_remap_top;

	unsigned long		lowmem_remap_base;
@@ -149,13 +152,31 @@ struct uv_hub_info_s { 
	unsigned char		m_val;

	unsigned char		n_val;

	struct uv_scir_s	scir;

	unsigned char		apic_pnode_shift;

};



DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);

#define uv_hub_info		(&__get_cpu_var(__uv_hub_info))

#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))



/*

 * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2

 * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.

 * This is a software convention - NOT the hardware revision numbers in

 * the hub chip.

 */

#define UV1_HUB_REVISION_BASE		1

#define UV2_HUB_REVISION_BASE		3



static inline int is_uv1_hub(void)

{

	return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;

}



static inline int is_uv2_hub(void)

{

	return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;

}



union uvh_apicid {

    unsigned long       v;

    struct uvh_apicid_s {
@@ -180,11 +201,25 @@ union uvh_apicid { 
#define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)

#define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)



#define UV_LOCAL_MMR_BASE		0xf4000000UL

#define UV_GLOBAL_MMR32_BASE		0xf8000000UL

#define UV1_LOCAL_MMR_BASE		0xf4000000UL

#define UV1_GLOBAL_MMR32_BASE		0xf8000000UL

#define UV1_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)

#define UV1_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)



#define UV2_LOCAL_MMR_BASE		0xfa000000UL

#define UV2_GLOBAL_MMR32_BASE		0xfc000000UL

#define UV2_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)

#define UV2_GLOBAL_MMR32_SIZE		(32UL * 1024 * 1024)



#define UV_LOCAL_MMR_BASE		(is_uv1_hub() ? UV1_LOCAL_MMR_BASE     \

						: UV2_LOCAL_MMR_BASE)

#define UV_GLOBAL_MMR32_BASE		(is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE  \

						: UV2_GLOBAL_MMR32_BASE)

#define UV_LOCAL_MMR_SIZE		(is_uv1_hub() ? UV1_LOCAL_MMR_SIZE :   \

						UV2_LOCAL_MMR_SIZE)

#define UV_GLOBAL_MMR32_SIZE		(is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\

						UV2_GLOBAL_MMR32_SIZE)

#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)

#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)

#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)



#define UV_GLOBAL_GRU_MMR_BASE		0x4000000
@@ -300,6 +335,17 @@ static inline int uv_apicid_to_pnode(int apicid) 
	return (apicid >> uv_hub_info->apic_pnode_shift);

}



/*

 * Convert an apicid to the socket number on the blade

 */

static inline int uv_apicid_to_socket(int apicid)

{

	if (is_uv1_hub())

		return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;

	else

		return 0;

}



/*

 * Access global MMRs using the low memory MMR32 space. This region supports

 * faster MMR access but not all MMRs are accessible in this space.
@@ -519,14 +565,13 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 


/*

 * Get the minimum revision number of the hub chips within the partition.

 *     1 - initial rev 1.0 silicon

 *     2 - rev 2.0 production silicon

 *     1 - UV1 rev 1.0 initial silicon

 *     2 - UV1 rev 2.0 production silicon

 *     3 - UV2 rev 1.0 initial silicon

 */

static inline int uv_get_min_hub_revision_id(void)

{

	extern int uv_min_hub_revision_id;



	return uv_min_hub_revision_id;

	return uv_hub_info->hub_revision;

}



#endif /* CONFIG_X86_64 */